公开(公告)号：US20140217467A1

公开(公告)日：2014-08-07

申请号：US13758225

申请日：2013-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

IPC: H01L21/02 ,  H01L29/12

CPC classification number: H01L29/12 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211

Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.

Abstract translation: 在第一和第二层之间获得由第一半导体材料的第一和第二层和应变释放缓冲层（SRB）层组成的结构，在第二层的开口的侧壁上形成侧壁间隔物，并形成第三半导体 所述开口中的材料，其中所述第一，第二和第三半导体材料是不同的。 一种器件包括第一和第二层第一和第二半导体材料以及位于第一层之上的SRB层。 第二层位于SRB层的第一部分之上，第三半导体材料的区域位于第二层的开口中并且位于SRB层的第二部分之上，并且绝缘材料位于由 第三半导体材料和第二层。

公开(公告)号：US09716177B2

公开(公告)日：2017-07-25

申请号：US14983217

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak ,  Behtash Behin-Aein ,  Mehdi Salmani-Jelodar

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/201

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/6681

Abstract: The device disclosed herein includes, among other things, a substrate made of a first semiconductor material, at least one layer of insulating material positioned above the substrate, a fin structure positioned above the layer of insulating material and the substrate, the fin structure including first, second and third layers of semiconductor material, wherein the semiconductor materials of the first, second and third layers are different than the first semiconductor material, and a gate structure around a portion of the fin structure includes the first, second and third layers of semiconductor material.

公开(公告)号：US09711644B2

公开(公告)日：2017-07-18

申请号：US14853073

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L29/66 ,  H01L29/772 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming a liner semiconductor material within a trench, the liner material defining a transistor cavity, and forming spaced-apart source/drain placeholder structures that are at least partially positioned within the transistor cavity, the spaced-apart source/drain placeholder structures defining a gate cavity therebetween where a portion of the liner semiconductor material is exposed within the gate cavity. The method further includes forming a gate structure within the gate cavity and, after forming the gate structure, removing at least a portion of the source/drain placeholder structures to define a plurality of source/drain cavities within the transistor cavity on opposite sides of the gate structure, and forming a source/drain structure in each of the source drain cavities.

公开(公告)号：US20170154994A1

公开(公告)日：2017-06-01

申请号：US14953874

申请日：2015-11-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/265 ,  H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/761

CPC classification number: H01L29/7827 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0646 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666

Abstract: One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a semiconductor substrate, the semiconductor structure comprising a lower source/drain region and an upper source/drain region, wherein the lower source/drain region physically contacts the upper surface of the substrate, forming a counter-doped isolation region in the substrate, forming a metal silicide region in the substrate above the counter-doped isolation region, wherein the metal silicide region is in physical contact with the lower source/drain region, and forming a lower source/drain contact structure that is conductively coupled to the metal silicide region.

公开(公告)号：US09601379B1

公开(公告)日：2017-03-21

申请号：US14757996

申请日：2015-12-23

Applicant: GLOBALFOUNDRIES Inc. ,  IMEC VZW

Inventor： Bartlomiej Jan Pawlak ,  Dmitry Yakimets ,  Pieter Schuddinck

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L23/532 ,  H01L27/088

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L29/0653 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: In one example, the method disclosed herein includes, among other things, forming a sacrificial structure around a plurality of stacked substantially un-doped nanowires at a location that corresponds to the channel region of the device, performing a selective etching process through a cavity to remove a second plurality of nanowires from the channel region and the source/drain regions of the device while leaving a first plurality of nanowires in position, and forming a metal conductive source/drain contact structure in each of the source/drain regions, wherein each of the metal conductive source/drain contact structures is positioned all around the first plurality of nanowires positioned in the source/drain regions.

公开(公告)号：US09263555B2

公开(公告)日：2016-02-16

申请号：US14322987

申请日：2014-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak ,  Behtash Behin-Aein ,  Mehdi Salmani-Jelodar

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/6681

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches that define a fin, performing a plurality of epitaxial deposition processes to form first, second and third layers of epi semiconductor material around an exposed portion of the fin, removing the first, second and third layers of epi semiconductor material from above an upper surface of the fin so as to thereby expose the fin, selectively removing the fin relative to the first, second and third layers of epi semiconductor material so as to thereby define two fin structures comprised of the first, second and third layers of epi semiconductor material, and forming a gate structure around a portion of at least one of the fin structures comprised of the first, second and third layers of epi semiconductor material.

Abstract translation: 本文公开的一种说明性方法包括形成限定翅片的多个沟槽，执行多个外延沉积工艺以在翅片的暴露部分周围形成第一，第二和第三层外延半导体材料，除去 第一层，第二层和第三层外延半导体材料，从翅片的上表面上方，从而露出翅片，相对于第一，第二和第三层外延半导体材料选择性地去除翅片，从而限定两个鳍 由第一层，第二层和第三层外延半导体材料构成的结构，以及围绕由第一，第二和第三层外延半导体材料构成的至少一个鳍结构的一部分形成栅极结构。