公开(公告)号：US10916642B2

公开(公告)日：2021-02-09

申请号：US16388500

申请日：2019-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US10367083B2

公开(公告)日：2019-07-30

申请号：US15081443

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L21/762 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US20190181250A1

公开(公告)日：2019-06-13

申请号：US16278268

申请日：2019-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L29/08 ,  H01L21/762 ,  H01L29/417 ,  H01L29/73 ,  H01L29/10 ,  H01L29/06

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US20190081597A1

公开(公告)日：2019-03-14

申请号：US15701672

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Alvin J. Joseph ,  John J. Pekarik

IPC: H03F1/22 ,  H01L27/07 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06

Abstract: Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.

公开(公告)号：US20180226292A1

公开(公告)日：2018-08-09

申请号：US15425384

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76289 ,  H01L21/6835 ,  H01L21/76283 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/7317 ,  H01L29/7371 ,  H01L29/78 ,  H01L2221/68345

Abstract: Structures with trench isolation and methods for making a structure with trench isolation. A transistor is formed by front-end-of-line processing on a first surface of a semiconductor substrate. A barrier layer is formed by middle-of-line processing on the transistor and the first surface of the semiconductor substrate. After the transistor and the barrier layer are formed, a trench is etched into the semiconductor substrate from a second surface of the semiconductor substrate that is opposite from the first surface of the semiconductor substrate. The trench, which is used to form an isolation region, may terminate on a dielectric layer associated with the transistor or may terminate on the barrier layer.

公开(公告)号：US09496377B2

公开(公告)日：2016-11-15

申请号：US14747525

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Peng Cheng ,  Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/732 ,  H01L29/73 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/7371

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.

公开(公告)号：US20160225917A1

公开(公告)日：2016-08-04

申请号：US15092976

申请日：2016-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： James W. Adkisson ,  James S. Dunn ,  Blaine J. Gross ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/808 ,  G06F17/50 ,  H01L29/161 ,  H01L29/06 ,  H01L29/47

CPC classification number: H01L29/808 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  H01L21/28026 ,  H01L21/306 ,  H01L21/8232 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66901 ,  H01L29/66924 ,  H01L29/7782 ,  H01L29/8124

Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

公开(公告)号：US09312370B2

公开(公告)日：2016-04-12

申请号：US14300944

申请日：2014-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  David L. Harame ,  Michael L. Kerbaugh ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/73 ,  H01L29/732 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/732 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7327 ,  H01L29/7371 ,  H01L29/7378

Abstract: The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.

Abstract translation: 本公开涉及集成电路（IC）结构及其形成方法。 根据本公开的IC结构可以包括：与绝缘区域相邻的掺杂衬底区域; 晶体基底结构，其包括：位于掺杂衬底区域上并与其接触的本征基极区域，本征基极区域具有第一厚度; 与所述绝缘区域相邻的外部基极区域，其中所述非本征基极区域具有大于所述第一厚度的第二厚度; 位于所述晶体基底结构的本征基极区上的半导体层; 以及位于半导体层上的掺杂半导体层。