公开(公告)号：US10909443B2

公开(公告)日：2021-02-02

申请号：US16283887

申请日：2019-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Siva P. Adusumilli ,  Ruilong Xie ,  Julien Frougier

IPC: G06N3/04 ,  H01L27/24 ,  H01L45/00 ,  H01L29/872

Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

公开(公告)号：US10903207B2

公开(公告)日：2021-01-26

申请号：US16258714

申请日：2019-01-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L49/02 ,  H01L29/08 ,  H01L29/45 ,  H01L29/06 ,  H01L27/12 ,  H01L27/105 ,  H01L21/02 ,  H01L21/265 ,  H01L27/088

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US10833183B2

公开(公告)日：2020-11-10

申请号：US16177877

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joshua Dillon ,  Siva P. Adusumilli ,  Jagar Singh ,  Anthony Stamper ,  Laura Schutz

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/872

Abstract: One device disclosed herein includes, among other things, first and second conductive features embedded in a first dielectric layer, a cap layer positioned above the first dielectric layer, a ballistic transport material contacting the first conductive member and positioned above a portion of the first dielectric layer, and first and second contacts contacting the first and second conductive features.

公开(公告)号：US10818763B1

公开(公告)日：2020-10-27

申请号：US16405368

申请日：2019-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Michel J. Abou-Khalil ,  Siva P. Adusumilli

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.

公开(公告)号：US10411107B2

公开(公告)日：2019-09-10

申请号：US15693537

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laura J. Schutz ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Joshua F. Dillon

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/423 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L21/28

Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.

公开(公告)号：US10393960B1

公开(公告)日：2019-08-27

申请号：US15905165

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/136 ,  G02B6/132 ,  G02B6/13

Abstract: Waveguide structures and methods of fabricating waveguide structures. A first airgap is formed in a bulk semiconductor substrate, and a semiconductor layer is epitaxially grown over the bulk semiconductor substrate and the first airgap. First and second trench isolation regions extend through the semiconductor layer and into the bulk semiconductor substrate, and are spaced to define a waveguide core region including a section of the bulk semiconductor substrate and a section of the semiconductor layer that are arranged between the first and second trench isolation regions. A dielectric layer is formed over the waveguide core region, and a second airgap is formed in the dielectric layer. The first airgap is arranged in the bulk semiconductor substrate between the first trench isolation region and the second trench isolation region and under the waveguide core region. The second airgap in the dielectric layer is arranged over the waveguide core region.

公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US10156676B1

公开(公告)日：2018-12-18

申请号：US15905134

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/136 ,  G02B6/12 ,  H01L31/0232 ,  H01L31/113

Abstract: Waveguide structures and methods of fabricating waveguide structures. The waveguide structures are formed using a semiconductor substrate that includes a device layer, a handle wafer, a buried oxide layer between the handle wafer and the device layer, and an epitaxial semiconductor layer over the device layer. First and second trench isolation regions extend through the device layer and the epitaxial semiconductor layer. The first and second trench isolation regions are spaced to define a waveguide core region comprising a section of the device layer and a section of the epitaxial semiconductor layer that are arranged between the first and second trench isolation regions. A first airgap and a second airgap are respectively located in the device layer and the buried oxide layer. The first and second airgaps are arranged beneath the waveguide core region, and the first airgap may be arranged between the second airgap and the waveguide core region.

公开(公告)号：US10833072B1

公开(公告)日：2020-11-10

申请号：US16404161

申请日：2019-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Mark Levy ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L27/082 ,  H01L29/737 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8222 ,  H01L21/225 ,  H01L21/311 ,  H01L27/06 ,  H01L21/762 ,  H01L23/544

Abstract: Structures for a heterojunction bipolar transistor and methods of fabricating such structures. A hardmask is formed that includes an opening over a first portion of a substrate in a first device region and a shape over a second portion of the substrate in a second device region. An oxidized region in the first portion of the substrate while the shape blocks oxidation of the second portion of the substrate. The oxidized region is subsequently removed from the first portion of the substrate to define a recess. A first base and a first emitter of a first heterojunction bipolar transistor are formed over the first portion of the substrate in the first device region, and a second base and a second emitter of a second heterojunction bipolar transistor are formed in the recess over the second portion of the substrate in the second device region.

公开(公告)号：US10832940B2

公开(公告)日：2020-11-10

申请号：US16218868

申请日：2018-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32 ,  H01L21/02 ,  H01L27/06 ,  H01L29/10

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.