公开(公告)号：US20170256449A1

公开(公告)日：2017-09-07

申请号：US15062328

申请日：2016-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Vimal Kamineni

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53209 ,  H01L23/53238

Abstract: One illustrative method disclosed herein includes, among other things, forming a first trench and a second trench in a layer of insulating material, the first trench having a first lateral critical dimension, the second trench having a second lateral critical dimension that is greater than the first lateral critical dimension of the first trench, forming a first conductive structure in the first trench, wherein a first bulk metal material constitutes a bulk portion of the first conductive structure, and forming a second conductive structure in the second trench, wherein a second bulk metal material constitutes a bulk portion of the second conductive structure and wherein the first bulk metal material and second bulk metal material are different materials.

公开(公告)号：US09613817B1

公开(公告)日：2017-04-04

申请号：US15138311

申请日：2016-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Vimal Kamineni

IPC: H01L21/285 ,  H01L21/8238

CPC classification number: H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823871

Abstract: A method of enhancing surface diffusion species concentration in source/drain regions includes providing a substrate for an integrated circuit. One of an n-type and a p-type S/D region for a semiconductor device is formed on a surface of the substrate. A top surface of the S/D region is exposed. A diffusion layer is deposited over the top surface of the S/D region, the diffusion layer having a concentration of a diffusion species. The diffusion layer is heated to diffuse the diffusion species into the S/D region to enhance a concentration of the diffusion species proximate the top surface of the S/D region. The diffusion layer is removed from the top surface of the S/D region. A metal layer is deposited over the top surface of the S/D region immediately after removing the diffusion layer. Electrical contacts are formed over the top surface of the S/D region from the metal layer.

公开(公告)号：US09570344B2

公开(公告)日：2017-02-14

申请号：US14752210

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal Kamineni ,  Nicholas Vincent Licausi ,  Shariq Siddiqui ,  Jeremy Austin Wahl

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76805 ,  H01L21/76814 ,  H01L23/535

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract translation: 一种方法可以包括在半导体结构中形成接触沟槽，使得接触沟槽延伸到接触层，形成包括使用硬掩模层，并用牺牲材料层填充接触沟槽，牺牲材料层形成在触点上 形成。 半导体结构可以包括在接触层上的牺牲材料层。

公开(公告)号：US20160190274A1

公开(公告)日：2016-06-30

申请号：US15059481

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal Kamineni ,  William J. Taylor

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/4975 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/41758 ,  H01L29/78 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a first epi semiconductor material positioned in a source/drain region of the device, the first epi semiconductor material having a first lateral width at an upper surface thereof. An extended-height epi contact structure having an upper surface and first and second side surfaces is positioned on the first epi semiconductor material, the upper surface and the first and second side surfaces collectively defining a contact length of the extended-height epi contact structure that is greater than the first lateral width. A metal silicide region is positioned on the upper surface and the first and second side surfaces of the extended-height epi contact structure.

Abstract translation: 一种器件包括位于器件的源极/漏极区域中的第一外延半导体材料，第一外延半导体材料在其上表面具有第一横向宽度。 具有上表面和第一和第二侧表面的延伸高度外延接触结构位于第一外延半导体材料上，上表面和第一和第二侧表面共同限定了延伸高度外延接触结构的接触长度， 大于第一横向宽度。 金属硅化物区域位于扩展高度外延接触结构的上表面和第一和第二侧表面上。

公开(公告)号：US09287213B2

公开(公告)日：2016-03-15

申请号：US14695965

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Xuan Lin ,  Vimal Kamineni

IPC: H01L21/31 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53266 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with improved contact structures are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate disposed with a device therein and/or thereon. The integrated circuit includes a contact structure in electrical contact with the device. The contact structure includes a plug metal and a barrier layer, and the barrier layer is selected from fluorine-free tungsten (FFW), tungsten carbide, and tungsten nitride. The integrated circuit further includes a dielectric material overlying the semiconductor substrate. Also, the integrated circuit includes an interconnect formed within the dielectric material and in electrical contact with the contact structure.

Abstract translation: 提供了具有改进的接触结构的集成电路。 在示例性实施例中，集成电路包括在其中和/或其上设置有设备的半导体衬底。 集成电路包括与器件电接触的接触结构。 接触结构包括插塞金属和阻挡层，阻挡层选自无氟钨（FFW），碳化钨和氮化钨。 集成电路还包括覆盖半导体衬底的电介质材料。 此外，集成电路包括形成在电介质材料内并与接触结构电接触的互连。

公开(公告)号：US09029920B2

公开(公告)日：2015-05-12

申请号：US13909328

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Vimal Kamineni ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section.

Abstract translation: 提供具有减小的栅极和/或接触电阻的半导体结构和制造方法。 该方法包括：提供半导体器件，其包括形成半导体器件的晶体管，其中晶体管形成包括：形成用于晶体管的T形栅极，T形栅极呈垂直截面为T形; 并且在晶体管的有源区域形成倒T形的接触，所述倒T形接触件包括在横截面上具有倒T形的导电结构。

公开(公告)号：US20200168504A1

公开(公告)日：2020-05-28

申请号：US16778884

申请日：2020-01-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Ruilong Xie ,  Mark Raymond

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/417

Abstract: Methods comprising forming a cobalt formation on an active feature of a semiconductor device, wherein the semiconductor device comprises an inactive feature above the cobalt formation; forming a cap on the cobalt formation; removing at least a portion of the inactive feature, wherein the cobalt formation is substantially not removed; forming a dielectric material above the cap; and forming a first contact to the cobalt formation. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US09905473B1

公开(公告)日：2018-02-27

申请号：US15598447

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Vimal Kamineni ,  Michael Aquilino

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545

Abstract: A method of fabricating a FinFET device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate (RMG) module. In particular, the method involves forming a sacrificial gate over the channel region of a fin, and an interlayer dielectric over adjacent source/drain regions of the fin. An etch mask is then used to protect source/drain contact regions and enable the removal of the interlayer dielectric from outside of the protected area, e.g., between adjacent fins. A sacrificial cobalt layer is used to backfill the cavities formed by etching the interlayer dielectric prior to forming a functional gate.

公开(公告)号：US20170170118A1

公开(公告)日：2017-06-15

申请号：US15251804

申请日：2016-08-30

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Su Chen Fan ,  Vimal Kamineni ,  Andre P. Labonte ,  Ruilong Xie

IPC: H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L23/535

Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.

公开(公告)号：US20170148669A1

公开(公告)日：2017-05-25

申请号：US14948214

申请日：2015-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vimal Kamineni ,  Mark V. Raymond ,  Praneet Adusumilli ,  Chengyu Niu

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/67207 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/45 ,  H01L29/78

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.