公开(公告)号：US09536784B1

公开(公告)日：2017-01-03

申请号：US14749843

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mukta G. Farooq ,  Andrew J. Martin ,  Jennifer A. Oakley

IPC: H01L21/78 ,  H01L21/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481

Abstract: A method of forming through silicon vias (TSVs) on integrated circuit (IC) chips and the IC chips. A TSV pattern on a stack of wiring layers on the surface of the IC chip identifies TSV locations. Etching the IC chip TSV pattern opens a cup shaped through hole through the stack to the silicon substrate at each TSV pattern location. The etched stack forms a TSV hard mask open (HMO) for the silicon substrate. Via through holes etched through the silicon substrate masked by the HMO are filled with conductor connecting IC circuits, e.g., to signal lines on the bottom of the chip.

Abstract translation: 一种在集成电路（IC）芯片和IC芯片上形成硅通孔（TSV）的方法。 在IC芯片表面上的一层布线层上的TSV图案标识TSV位置。 蚀刻IC芯片TSV图案在每个TSV图案位置处通过堆叠打开杯形通孔到硅衬底。 蚀刻的堆叠形成用于硅衬底的TSV硬掩模开口（HMO）。 蚀刻通过由HMO掩蔽的硅衬底的通孔穿过IC连接IC电路，例如连接到芯片底部的信号线。

公开(公告)号：US09252133B2

公开(公告)日：2016-02-02

申请号：US14487439

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christopher N. Collins ,  Mukta G. Farooq ,  Troy L. Graves-Abe ,  Joyce C. Liu ,  Gerd Pfeiffer ,  Thuy L. Tran-Quinn

IPC: H01L23/00 ,  H01L25/065 ,  H01L29/32 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/5384 ,  H01L29/32 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).

Abstract translation: 已经证明用于3D应用的TSV（通过衬底通孔）的形成缺陷取决于所采用的起始半导体衬底的类型。 除了通过博世处理初始形成TSV之外，背面3D晶片处理也显示了对衬底类型的缺陷依赖性。 可以通过利用以1e4 / cc（每立方厘米颗粒）和1e7 / cc之间的密度并且具有小于55nm（纳米）的当量直径的体积微观缺陷（BMD）来实现高产率的TSV形成。

公开(公告)号：US20200066667A1

公开(公告)日：2020-02-27

申请号：US16106239

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Tanya A. Atanasova

IPC: H01L23/00

Abstract: The disclosure is directed to an integrated circuit structure for joining wafers. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material.

公开(公告)号：US10296698B2

公开(公告)日：2019-05-21

申请号：US15378122

申请日：2016-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Troy L. Graves-Abe

IPC: G06F17/50 ,  H01L21/768

Abstract: Various embodiments include approaches for designing through-silicon vias (TSVs) in integrated circuits (ICs). In some cases, a method includes: identifying types of through-silicon vias (TSVs) for placement within an integrated circuit (IC) design based upon an electrical requirement for the TSVs, wherein the IC design includes distinct types of TSVs; calculating etch and fill rates for the IC design with the distinct types of TSVs with common etching and filling processes; and providing fabrication instructions to form the distinct types of TSVs according to the calculated etch and fill rates in the common processes.

公开(公告)号：US10276461B2

公开(公告)日：2019-04-30

申请号：US15665974

申请日：2017-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ian D. W. Melville ,  Mukta G. Farooq

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00

Abstract: A structure and method for forming a split probe pad structure for a semiconductor structure. The split probe pad structure may include a first probe pad structure over a substrate, the first probe pad structure including a first probe pad in electrical communication with the substrate; a second probe pad structure over the substrate, the second probe pad structure including a second probe pad in electrical communication with the substrate, wherein the second probe pad structure is laterally separated from the first probe pad structure; and a non-metal region between the first probe pad structure and the second probe pad structure. The split probe pad structure may be formed in a kerf region of the semiconductor structure. The non-metal region may include a dielectric material.

公开(公告)号：US10242947B2

公开(公告)日：2019-03-26

申请号：US15713756

申请日：2017-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L21/76 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US20180337089A1

公开(公告)日：2018-11-22

申请号：US16033932

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Ian D.W. Melville

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76841 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53276

Abstract: A method of forming an IC structure, including: forming a first plurality of active devices within a first semiconductor layer over a substrate; forming a first wiring layer over the first semiconductor layer, the first wiring layer including a first metal having a melting point greater than approximately 1400 degrees Celsius (° C.); forming a second semiconductor layer over the first wiring layer; forming a second plurality of active devices within the second semiconductor layer; and forming a second wiring layer over the second semiconductor layer, the second wiring layer including the first metal having a melting point greater than approximately 1400 degrees Celsius (° C.).

公开(公告)号：US20180012845A1

公开(公告)日：2018-01-11

申请号：US15713756

申请日：2017-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76251 ,  H01L21/76254 ,  H01L23/481 ,  H01L23/522 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147

Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

公开(公告)号：US09842810B1

公开(公告)日：2017-12-12

申请号：US15176595

申请日：2016-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ekta Misra ,  Mukta G. Farooq ,  Krishna Tunga

IPC: H01L23/00 ,  H01L21/3205 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/32051 ,  H01L23/3171 ,  H01L23/5283

Abstract: Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.

公开(公告)号：US20170162508A1

公开(公告)日：2017-06-08

申请号：US14957860

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta G. Farooq ,  Joyce C. Liu ,  Jennifer A. Oakley

IPC: H01L23/538 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L21/762 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0642

Abstract: Through-substrate vias (TSVs) include a strain engineering layer configured to minimize or otherwise control local stress fields. The strain engineering layer can be separate from and in addition to a TSV sidewall isolation layer that is deposited along the via sidewall surface for the purpose of electric isolation. For instance, the strain engineering layer can be a partial depth layer that extends over only a portion of the TSV sidewall.