公开(公告)号：US09224865B2

公开(公告)日：2015-12-29

申请号：US13945627

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.

Abstract translation: FinFET具有包括半导体衬底，半导体鳍片和横跨翅片的栅极的结构。 翅片各自具有连接到基底的底部区域和顶部活动区域。 位于底部和顶部翅片区域之间的是中间堆叠，位于垂直细长的源和垂直细长的排水管之间。 堆叠包括顶部通道区域和紧邻通道区域下方的电介质区域，提供通道的电隔离。 部分隔离结构可以与栅极第一和栅极末端制造工艺一起使用。

公开(公告)号：US20150056781A1

公开(公告)日：2015-02-26

申请号：US13971937

申请日：2013-08-21

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76264 ,  H01L21/02488 ,  H01L21/76224 ,  H01L29/66795

Abstract: Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.

Abstract translation: 提供了在具有与绝缘体与衬底隔离的有源沟道区的本体衬底上制造集成电路和FinFET晶体管的方法。 根据示例性实施例，一种用于制造集成电路的方法包括形成覆盖半导体衬底的鳍状结构，其中每个鳍结构包括沟道材料并且在纵向方向上从第一端延伸到第二端。 该方法将锚固材料沉积在翅片结构上。 该方法包括使锚固材料凹入以形成邻近翅片结构的沟槽，其中锚定材料保持与每个翅片结构的第一端和第二端接触。 此外，该方法在半导体衬底和每个鳍结构的沟道材料之间形成空隙，栅极长度独立蚀刻工艺，其中每个鳍结构的沟道材料悬置在半导体衬底上。

公开(公告)号：US20140361377A1

公开(公告)日：2014-12-11

申请号：US13914808

申请日：2013-06-11

Applicant: GLOBALFOUNDRIES Inc. ,  Renesas Electronics Corporation ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Steven John Bentley ,  Murat Kerem Akarvardar ,  Jody Alan Fronheiser ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 一组高迁移率通道散热片形成在逆向掺杂层上，该组高迁移率通道散热片中的每一个包括高迁移率通道材料（例如硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和一组高迁移率通道翅片之间的碳衬垫，以防止载流子溢出到高迁移率通道翅片。

公开(公告)号：US10062617B2

公开(公告)日：2018-08-28

申请号：US15373852

申请日：2016-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Murat Kerem Akarvardar ,  Andreas Knorr

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/762 ,  H01L21/308 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/823821 ,  H01L21/3083 ,  H01L21/3105 ,  H01L21/32105 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/7842 ,  H01L29/7849

Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.

公开(公告)号：US09847333B2

公开(公告)日：2017-12-19

申请号：US15051420

申请日：2016-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwanyong Lim ,  Murat Kerem Akarvardar

IPC: H01L29/16 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L29/167

Abstract: Reducing a chance of punch-through in a FinFET structure includes providing a substrate, creating a blanket layer of semiconductor material with impurities therein over the substrate, masking a portion of the blanket layer, creating epitaxial semiconductor material on an unmasked portion of the structure, removing the mask, and etching the structure to create n-type raised structure(s) and p-type raised structure(s), a bottom portion of the raised structure(s) being surrounded by isolation material. A middle portion of the raised structure(s) includes a semiconductor material with impurities therein, the middle portion extending across the raised structure(s), and a top portion including a semiconductor material lacking added impurities.

公开(公告)号：US09590040B2

公开(公告)日：2017-03-07

申请号：US14341000

申请日：2014-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/84 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7854

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial fin structure above a semiconductor substrate, forming a layer of insulating material around the sacrificial fin structure, removing the sacrificial fin structure so as to define a replacement fin cavity in the layer of insulating material that exposes an upper surface of the substrate, forming a replacement fin in the replacement fin cavity on the exposed upper surface of the substrate, recessing the layer of insulating material, and forming a gate structure around at least a portion of the replacement fin exposed above the recessed layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲鳍结构，在牺牲鳍结构周围形成绝缘材料层，去除牺牲鳍结构，以便在 绝缘材料，其暴露衬底的上表面，在所述衬底的暴露的上表面上的替换翅片腔中形成替换翅片，使所述绝缘材料层凹陷，以及在所述替换鳍片的至少一部分周围形成栅极结构 暴露在绝缘材料的凹陷层上方。

公开(公告)号：US09515088B1

公开(公告)日：2016-12-06

申请号：US15040278

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar

IPC: H01L27/11 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0924 ,  H01L27/1211 ,  H01L2027/11857 ,  H01L2027/11859

Abstract: A semiconductor structure is provided with fins on a substrate, including: a first active layer with a first source, first channel, and first drain, each doped with the same concentration of dopant as each other; a dielectric layer on the first active layer; a second active layer with a second source, second channel, and second drain, each doped with the same concentration of dopant as each other; and a first and second gate disposed on an opposing first and second sidewall of the channels, respectively. A method for making such a semiconductor structure is also provided.

Abstract translation: 半导体结构在衬底上设置有翅片，包括：具有第一源极，第一沟道和第一漏极的第一有源层，每个掺杂相同浓度的掺杂剂; 第一有源层上的介电层; 具有第二源极，第二沟道和第二漏极的第二有源层，每个掺杂有彼此相同浓度的掺杂物; 以及分别设置在通道的相对的第一和第二侧壁上的第一和第二门。 还提供了制造这种半导体结构的方法。

公开(公告)号：US09508848B1

公开(公告)日：2016-11-29

申请号：US15012184

申请日：2016-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L21/324

CPC classification number: H01L21/324 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, removing at least a portion of a vertical height of portions of an overall fin structure that are not covered by a gate structure so as to result in the definition of a remaining portion of the overall fin structure that is positioned under the gate structure, wherein the remaining portion comprises a channel portion and a lower portion located under the channel portion. The method continues with the formation of a layer of heat-expandable material (HEM), performing a heating process on the HEM so as to cause the HEM to expand, recessing the HEM so as to expose edges of the channel portion and growing a semiconductor material above the HEM using the exposed edges of the channel portion as a growth surface.

Abstract translation: 本文公开的一种说明性方法包括除去未被栅极结构覆盖的整个鳍结构的部分的垂直高度的至少一部分，以便导致整个鳍的剩余部分的定义 所述结构位于所述栅极结构下方，其中所述剩​​余部分包括通道部分和位于所述通道部分下方的下部。 该方法继续形成一层可热膨胀材料（HEM），对HEM进行加热处理，以使HEM膨胀，使HEM凹陷，从而暴露通道部分的边缘并生长半导体 使用通道部分的暴露边缘作为生长表面的HEM上方的材料。

公开(公告)号：US20160190323A1

公开(公告)日：2016-06-30

申请号：US14676239

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。

公开(公告)号：US20160133720A1

公开(公告)日：2016-05-12

申请号：US14535942

申请日：2014-11-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/02362 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/311 ,  H01L29/401 ,  H01L29/66553 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming at least one layer of insulating material with a substantially planar upper surface that is positioned above the upper surface of the fin, forming a layer of sacrificial gate material on the layer of insulating material, the layer of sacrificial gate material having an as-deposited upper surface and a substantially uniform thickness, forming a layer of gate cap material on the as-deposited upper surface of the layer of sacrificial gate material, forming a patterned sacrificial gate structure comprised of at least the gate cap material and the sacrificial gate material, forming a sidewall spacer adjacent the patterned sacrificial gate structure, removing the patterned sacrificial gate structure and replacing it with a replacement gate structure.

Abstract translation: 本文公开的一种说明性方法包括形成至少一层具有基本平坦的上表面的绝缘材料层，所述绝缘材料层位于鳍的上表面之上，在绝缘材料层上形成牺牲栅极材料层， 牺牲栅极材料层具有沉积的上表面和基本上均匀的厚度，在牺牲栅极材料层的沉积的上表面上形成栅极盖材料层，形成图案化的牺牲栅极结构，其包括在 至少栅极盖材料和牺牲栅极材料，形成邻近图案化的牺牲栅极结构的侧壁间隔物，去除图案化的牺牲栅极结构并用替代栅极结构代替。