中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

35 records (took 0.018 seconds)

    Dual metal-insulator-semiconductor contact structure and formulation method
    23.
    发明授权
    Dual metal-insulator-semiconductor contact structure and formulation method 有权

    公开(公告)号：US10535606B2

    公开(公告)日：2020-01-14

    申请号：US16040752

    申请日：2018-07-20

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

    Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

    IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L29/66

    Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

    DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD
    26.
    发明申请
    DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD 审中-公开

    公开(公告)号：US20200066638A1

    公开(公告)日：2020-02-27

    申请号：US16668409

    申请日：2019-10-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

    Inventor： Takashi Ando ,  Hiroaki Niimi ,  Tenko Yamashita

    IPC: H01L23/535 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L23/485 ,  H01L21/285

    Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

    FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS
    30.
    发明申请
    FIELD EFFECT TRANSISTORS HAVING MULTIPLE EFFECTIVE WORK FUNCTIONS 有权
    具有多种有效工作功能的场效应晶体管

    公开(公告)号：US20170047255A1

    公开(公告)日：2017-02-16

    申请号：US15338894

    申请日：2016-10-31

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Takashi Ando ,  Min Dai ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon

    IPC: H01L21/8234 ,  H01L21/324 ,  H01L21/8238

    CPC classification number: H01L21/823412 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/785

    Abstract: Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

    Abstract translation: 硅 - 锗表面层在半导体表面上的选择性沉积可用于为场效应晶体管提供两种类型的沟道区。 在硅基栅极电介质和高介电常数（高k）栅极电介质的堆叠上的调整氧化物材料的退火可以用于形成接触通道区域子集的界面调整氧化物层。 通过沉积第一功函数金属材料层和封盖层和随后的退火，可以在覆盖界面调整氧化物层的高k电介质层的部分中诱导氧缺乏。 可以通过物理暴露高k电介质层的部分来选择性地去除氧缺乏。 可以将第二功函数金属材料层和栅极导体层沉积并平坦化以形成提供多个有效功函数的栅电极。

Patent Agency Ranking