公开(公告)号：US20220181317A1

公开(公告)日：2022-06-09

申请号：US17113473

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Michel J. Abou-Khalil ,  John J. Ellis-Monaghan ,  Randy Wolf ,  Alvin J. Joseph ,  Aaron Vallett

IPC: H01L27/02 ,  H01L29/06

Abstract: Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

公开(公告)号：US11315825B2

公开(公告)日：2022-04-26

申请号：US16553737

申请日：2019-08-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.

公开(公告)号：US11791334B2

公开(公告)日：2023-10-17

申请号：US17075056

申请日：2020-10-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L27/08 ,  H01L27/082 ,  H01L27/06 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L27/082 ,  H01L27/0647 ,  H01L29/0646 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

公开(公告)号：US11740418B2

公开(公告)日：2023-08-29

申请号：US17209416

申请日：2021-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  John J. Ellis-Monaghan ,  Frank G. Kuechenmeister ,  Jae Kyu Cho ,  Michal Rakowski

IPC: G02B6/42 ,  H01L23/00 ,  G02B6/30 ,  G02B6/12

CPC classification number: G02B6/4248 ,  G02B6/30 ,  H01L23/562 ,  G02B2006/12119

Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.

公开(公告)号：US11543606B2

公开(公告)日：2023-01-03

申请号：US17196428

申请日：2021-03-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Jae Kyu Cho ,  Frank Kuechenmeister ,  John J. Ellis-Monaghan ,  Michal Rakowski

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/13 ,  F21V8/00

Abstract: Structures including an edge coupler and a crackstop, as well as methods of forming a structure including an edge coupler and a crackstop. A waveguide core and a crackstop are located over a top surface of a dielectric layer. A communication passageway is either optically coupled or electrically coupled to the waveguide core. The communication passageway, which may include an electric conductor or a buried waveguide core, extends laterally beneath the crackstop.

公开(公告)号：US11424377B2

公开(公告)日：2022-08-23

申请号：US17065862

申请日：2020-10-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Rajendran Krishnasamy ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Ramsey Hazbun

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/18 ,  H01L31/103 ,  H01L31/028

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photodiode with an integrated, light focusing elements and methods of manufacture. The structure includes: a trench photodiode comprising a domed structure; and a doped material on the domed structure, the doped material having a concave underside surface.

公开(公告)号：US11380622B2

公开(公告)日：2022-07-05

申请号：US16953441

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Sunil K. Singh ,  Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  John J. Ellis-Monaghan ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/00

Abstract: The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure.

公开(公告)号：US11322639B2

公开(公告)日：2022-05-03

申请号：US16844606

申请日：2020-04-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Vibhor Jain ,  Ramsey Hazbun ,  Pernell Dongmo ,  Cameron E. Luce ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L31/107 ,  H01L31/18 ,  H01L31/028 ,  H01L31/0376

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an avalanche photodiode and methods of manufacture. The structure includes: a substrate material having a trench with sidewalls and a bottom composed of the substrate material; a first semiconductor material lining the sidewalls and the bottom of the trench; a photosensitive semiconductor material provided on the first semiconductor material; and a third semiconductor material provided on the photosensitive semiconductor material.

公开(公告)号：US11316064B2

公开(公告)日：2022-04-26

申请号：US16887375

申请日：2020-05-29

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Mark D. Levy ,  Vibhor Jain ,  Andre Sturm

IPC: H01L31/107 ,  H01L31/105 ,  H01L31/036 ,  H01L31/028 ,  H01L31/0312

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.

公开(公告)号：US11296190B2

公开(公告)日：2022-04-05

申请号：US16743589

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L29/10 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/74

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.