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公开(公告)号：US09773547B2
公开(公告)日：2017-09-26
申请号：US15113914
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Richard H. Henze , Naveen Muralimanohar , Yoocharn Jeon , Martin Foltin , Erik Ordentlich , Gregg B. Lesartre , R. Stanley Williams
CPC classification number: G11C13/004 , G11C5/025 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L23/528 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.
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22.发明申请公开(公告)号：US20170271589A1
公开(公告)日：2017-09-21
申请号：US15329801
申请日：2015-01-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Minxian Max Zhang , Jianhua Yang , Zhiyong Li , R. Stanley Williams
CPC classification number: H01L45/146 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1633 , H01L45/1641
Abstract: A resistive memory array includes a plurality of resistive memory devices. A sneak path current in the resistive memory array is reduced when a negative temperature coefficient of resistance material is incorporated in series with a negative differential resistance selector that is in series with a memristor switching material at a junction formed at a cross-point between two conductors of one of the plurality of resistive memory devices.
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公开(公告)号：US20180314927A1
公开(公告)日：2018-11-01
申请号：US15770430
申请日：2015-10-30
Applicant: Hewlett Packard Enterprise Development LP
CPC classification number: G06N3/063 , G06N3/0635
Abstract: According to an example, a hybrid synaptic architecture based neural network may be implemented by determining, from input data, information that is to be recognized, mined, and/or synthesized by a plurality of analog neural cores. Further, the hybrid synaptic architecture based neural network may be implemented by determining, based on the information, selected ones of the plurality of analog neural cores that are to be actuated to identify a data subset of the input data to generate, based on the analysis of the data subset, results of the recognition, mining, and/or synthesizing of the information.
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公开(公告)号：US09842646B2
公开(公告)日：2017-12-12
申请号：US15500555
申请日：2015-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Miao Hu , Ning Ge , John Paul Strachan , R. Stanley Williams
CPC classification number: G11C13/004 , G06N3/049 , G06N3/0635 , G11C11/54 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C27/005 , G11C2213/74 , G11C2213/75 , G11C2213/76 , G11C2213/79
Abstract: In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.
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公开(公告)号：US20170271410A1
公开(公告)日：2017-09-21
申请号：US15500049
申请日：2015-02-11
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Minxian Max Zhang , Kathryn Samuels , Jianhua Joshua Yang , R. Stanley Williams , Zhiyong Li
IPC: H01L27/24
CPC classification number: H01L27/2418 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/14 , H01L45/146
Abstract: Provided in one example is a nonvolatile memory crossbar array. The array includes a number of junctions formed by a number of row lines intersecting a number of column lines; and a resistive memory element in series with a selector at each of the junctions coupling between one of the row lines and one of the column lines. The selector may be a volatile switch including: a bottom electrode; an oxide layer disposed over the bottom electrode, the oxide layer including Cu2O; and a top electrode disposed over the oxide layer.
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Patent Agency Ranking
公开(公告)号：US20170221558A1
公开(公告)日：2017-08-03
申请号：US15500555
申请日：2015-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Miao Hu , Ning Ge , John Paul Strachan , R. Stanley Williams
IPC: G11C13/00
CPC classification number: G11C13/004 , G06N3/049 , G06N3/0635 , G11C11/54 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C27/005 , G11C2213/74 , G11C2213/75 , G11C2213/76 , G11C2213/79
Abstract: In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.
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公开(公告)号：US20160351802A1
公开(公告)日：2016-12-01
申请号：US15111515
申请日：2014-01-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Warren Jackson , Gary Gibson , R. Stanley Williams , Jianhua Yang
CPC classification number: H01L45/12 , G11C13/003 , H01L27/2418 , H01L45/00
Abstract: A nonlinear dielectric stack circuit element includes a first layer of material having a first dielectric constant; a second layer of material having a second dielectric constant; and a third layer of material sandwiched between the first layer of material and the second layer of material and having a third dielectric constant. The third dielectric constant has a value less than the first dielectric constant and the second dielectric constant.
Abstract translation: 非线性介质堆叠电路元件包括具有第一介电常数的第一材料层; 具有第二介电常数的第二材料层; 以及夹在所述第一材料层和所述第二材料层之间并具有第三介电常数的第三材料层。 第三介电常数的值小于第一介电常数和第二介电常数。
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公开(公告)号：US20160350023A1
公开(公告)日：2016-12-01
申请号：US15106444
申请日：2014-01-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gregg B. Lesartre , R. Stanley Williams , Gary Gibson
IPC: G06F3/06
CPC classification number: G06F3/0632 , G06F3/0604 , G06F3/0616 , G06F3/0688 , G06F12/0238 , G06F2212/1036 , G11C13/0033 , G11C16/20 , G11C16/3418 , G11C2013/0083
Abstract: A system for re-initializing a memory array is described. The system includes a processor and a memory array communicatively coupled to the processor. The system also includes a memory manager. The memory manager includes an establish module to establish a reference state for the memory array. The reference state includes a number of target resistance values for the memory array. The memory manager includes a write module to write data to the memory array. The memory manager includes a re-initialize module to re-initialize the memory array to the established reference state.
Abstract translation: 描述用于重新初始化存储器阵列的系统。 该系统包括处理器和通信地耦合到处理器的存储器阵列。 该系统还包括一个内存管理器。 存储器管理器包括建立模块以建立存储器阵列的参考状态。 参考状态包括存储器阵列的多个目标电阻值。 存储器管理器包括用于将数据写入存储器阵列的写入模块。 存储器管理器包括重新初始化模块以将存储器阵列重新初始化为已建立的参考状态。
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公开(公告)号：US20160254448A1
公开(公告)日：2016-09-01
申请号：US15032913
申请日：2013-11-12
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Byungjoon Choi , Jianhua Yang , R. Stanley Williams , Gary Gibson , Warren Jackson
IPC: H01L45/00
CPC classification number: H01L45/1226 , H01L27/2418 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A nonlinear memristor device with a three-layer selector includes a memristor in electrical series with a three-layer selector. The memristor comprises at least one electrically conducting layer and at least one electrically insulating layer. The three-layer selector comprises a three-layer structure selected from the group consisting of XN—XO—XN; XN—YO—ZN: XN—YO—XN; XO—XN—XO; XO—YN—XO; XO—YN—ZO; XO—YO—XO; XO—YO—ZO; XN—YN—ZN; and XN—YN—XN, X represents a compound-forming metal different from Y and Z.
Abstract translation: 具有三层选择器的非线性忆阻器装置包括与三层选择器电连接的忆阻器。 忆阻器包括至少一个导电层和至少一个电绝缘层。 三层选择器包括从XN-XO-XN组成的组中选择的三层结构; XN-YO-ZN：XN-YO-XN; XO-XN-XO; XO-YN-XO; XO-YN-ZO; XO-YO-XO; XO-YO-ZO; XN-YN-ZN; 和XN-YN-XN，X表示不同于Y和Z的化合物形成金属。
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公开(公告)号：US20160225823A1
公开(公告)日：2016-08-04
申请号：US14916766
申请日：2013-09-16
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Shih-Yuan Wang , Jianhua Yang , R. Stanley Williams
CPC classification number: H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1683
Abstract: A switching resistance memory device with an interfacial channel includes a stack made of a layer of a first material and a layer of a second material. The layers form an interface, with the interface comprising the interfacial channel along which charged species can travel. A first electrode contacts a first edge of the stack, and a second electrode contacts a second edge of the stack.
Abstract translation: 具有界面通道的开关电阻存储器件包括由第一材料层和第二材料层构成的叠层。 这些层形成界面，其界面包括带电物种可以沿其移动的界面通道。 第一电极接触堆叠的第一边缘，并且第二电极接触堆叠的第二边缘。
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