公开(公告)号：US07663921B2

公开(公告)日：2010-02-16

申请号：US12267519

申请日：2008-11-07

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/04

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.

摘要翻译： 公开了包括排列在扇区中的存储单元的系统和方法。 在一个示例性实施方案中，每个存储单元可以包括顶部栅极，源极，耦合扇区中的存储器单元的顶栅极线和将存储器单元耦合在一起的字线。 此外，顶栅线可以动态耦合到字线。 其它示例性实现可涉及用于驱动字线和/或顶栅线，多电平存储器单元和/或浮栅线特征的驱动器。

公开(公告)号：US07567458B2

公开(公告)日：2009-07-28

申请号：US11235901

申请日：2005-09-26

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/34

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

摘要翻译： 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。

公开(公告)号：US20090067239A1

公开(公告)日：2009-03-12

申请号：US12267519

申请日：2008-11-07

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/00 ,  G11C16/06

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

公开(公告)号：US20090052248A1

公开(公告)日：2009-02-26

申请号：US12200930

申请日：2008-08-28

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC分类号： G11C16/34 ,  G11C16/06 ,  G11C29/00

CPC分类号： G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

公开(公告)号：US20080239834A1

公开(公告)日：2008-10-02

申请号：US11942665

申请日：2007-11-19

申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

IPC分类号： G01R19/00 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062

摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

摘要翻译： 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。

公开(公告)号：US08811093B2

公开(公告)日：2014-08-19

申请号：US13419269

申请日：2012-03-13

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3418

摘要： An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.

摘要翻译： 在第一导电类型的半导体衬底中的非易失性存储单元阵列。 每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域，其间具有沟道区域。 字线重叠在通道区域的一部分上，与第一区域相邻，并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的另一部分，并且与第一部分和第二区域相邻。 耦合栅极覆盖浮栅。 擦除门覆盖第二区域。 位线连接到第一区域。 负电荷泵电路产生负电压。 控制电路响应于接收到命令信号而产生多个控制信号，并将负电压施加到未选择存储单元的字线。

公开(公告)号：US20130148428A1

公开(公告)日：2013-06-13

申请号：US13315213

申请日：2011-12-08

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C7/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2263 ,  G11C2211/5647 ,  H01L27/11517

摘要： A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

公开(公告)号：US07405988B2

公开(公告)日：2008-07-29

申请号：US11235894

申请日：2005-09-26

申请人： Hieu Van Tran ,  Hung Quoc Nguyen

发明人： Hieu Van Tran ,  Hung Quoc Nguyen

IPC分类号： G11C7/02

CPC分类号： G11C16/28 ,  G11C7/02 ,  G11C7/062 ,  G11C7/08 ,  G11C11/5642 ,  G11C16/30

摘要： Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.

摘要翻译： 公开了用于存储器感测系统的随机或系统失配补偿的方法和装置。 感测放大器包括用于将感测晶体管的体积设置为不同于驱动感测晶体管的电压的电压的体电压源。 对于NMOS感测晶体管，使用三重阱作为可变体电压。 包括各种偏移补偿的差分放大器。 有意义的意图偏移创建也包括在内。

公开(公告)号：US09472284B2

公开(公告)日：2016-10-18

申请号：US13680719

申请日：2012-11-19

申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Mark Reiten

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  G11C29/26 ,  G11C16/04 ,  G11C16/26 ,  G11C7/04 ,  G11C29/02 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

CPC分类号： G11C29/76 ,  G11C5/02 ,  G11C5/06 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/26 ,  G11C2213/71 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311

摘要： A three-dimensional flash memory system is disclosed.

摘要翻译： 公开了三维闪存系统。

公开(公告)号：US20080224774A1

公开(公告)日：2008-09-18

申请号：US12131008

申请日：2008-05-30

申请人： Hieu Van Tran ,  Hung Quoc Nguyen

发明人： Hieu Van Tran ,  Hung Quoc Nguyen

IPC分类号： H03F3/45

CPC分类号： G11C16/28 ,  G11C7/02 ,  G11C7/062 ,  G11C7/08 ,  G11C11/5642 ,  G11C16/30

摘要： Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.

摘要翻译： 公开了用于存储器感测系统的随机或系统失配补偿的方法和装置。 感测放大器包括用于将感测晶体管的体积设置为不同于驱动感测晶体管的电压的电压的体电压源。 对于NMOS感测晶体管，使用三重阱作为可变体电压。 包括各种偏移补偿的差分放大器。 有意义的意图偏移创建也包括在内。