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47 条记录 (耗时 0.025 秒)

    Mixed voltage non-volatile memory integrated circuit with power saving
    3.
    发明授权
    Mixed voltage non-volatile memory integrated circuit with power saving 有权
    混合电压非易失性存储器集成电路，省电

    公开(公告)号：US08705282B2

    公开(公告)日：2014-04-22

    申请号：US13286969

    申请日：2011-11-01

    申请人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/08

    摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.

    摘要翻译： 集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。 第二电压小于第一电压。 可在第一电压下操作的第一电路在集成电路管芯中。 可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。 检测来自第二管芯焊盘的电流的电路在集成电路管芯中。 开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

    Non-volatile Memory Device And A Method Of Operating Same
    4.
    发明申请
    Non-volatile Memory Device And A Method Of Operating Same 有权
    非易失性存储器件及其操作方法相同

    公开(公告)号：US20130242672A1

    公开(公告)日：2013-09-19

    申请号：US13419269

    申请日：2012-03-13

    申请人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    发明人： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC分类号： G11C16/04

    CPC分类号： G11C16/04 ,  G11C16/0425 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3418

    摘要： An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.

    摘要翻译： 在第一导电类型的半导体衬底中的非易失性存储单元阵列。 每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域，其间具有沟道区域。 字线重叠在通道区域的一部分上，与第一区域相邻，并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的另一部分，并且与第一部分和第二区域相邻。 耦合栅极覆盖浮栅。 擦除门覆盖第二区域。 位线连接到第一区域。 负电荷泵电路产生负电压。 控制电路响应于接收到命令信号而产生多个控制信号，并将负电压施加到未选择存储单元的字线。

    Charge pump systems and methods
    5.
    发明授权
    Charge pump systems and methods 有权

    公开(公告)号：US08339187B2

    公开(公告)日：2012-12-25

    申请号：US13070405

    申请日：2011-03-23

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    IPC分类号： H02M3/18 ,  G05F3/20

    CPC分类号： G05F3/02 ,  H02M3/073 ,  H02M2001/322

    摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

    Sense amplifier for low voltage high speed sensing
    7.
    发明授权
    Sense amplifier for low voltage high speed sensing 有权
    用于低电压高速感应的感应放大器

    公开(公告)号：US07616028B2

    公开(公告)日：2009-11-10

    申请号：US11942665

    申请日：2007-11-19

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    IPC分类号： G01R19/00

    CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062

    摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

    摘要翻译： 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。

    CHARGE PUMP SYSTEMS AND METHODS
    9.
    发明申请
    CHARGE PUMP SYSTEMS AND METHODS 有权
    充电泵系统和方法

    公开(公告)号：US20110169558A1

    公开(公告)日：2011-07-14

    申请号：US13070405

    申请日：2011-03-23

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Nasrin Jaffari ,  Hung Quoc Nguyen ,  Anh Ly

    IPC分类号： G05F1/10

    CPC分类号： G05F3/02 ,  H02M3/073 ,  H02M2001/322

    摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

    摘要翻译： 数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。 电荷泵可以包括多个泵级。 示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。 其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。 每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。 另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲， 预充电电路。

    SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING
    10.
    发明申请
    SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
    用于低电压高速感应的感应放大器

    公开(公告)号：US20110121863A1

    公开(公告)日：2011-05-26

    申请号：US12972974

    申请日：2010-12-20

    申请人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    发明人： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

    IPC分类号： G11C7/08 ,  H03F3/45 ,  G11C7/06

    CPC分类号： G11C11/5642 ,  G11C7/06 ,  G11C7/062

    摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

    摘要翻译： 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。