公开(公告)号：US20060017086A1

公开(公告)日：2006-01-26

申请号：US11223958

申请日：2005-09-13

申请人： Hiroyuki Kanaya ,  Iwao Kunishima ,  Koji Yamakawa ,  Tsuyoshi Iwamoto ,  Hiroshi Mochizuki ,  Yoshinori Kumura

发明人： Hiroyuki Kanaya ,  Iwao Kunishima ,  Koji Yamakawa ,  Tsuyoshi Iwamoto ,  Hiroshi Mochizuki ,  Yoshinori Kumura

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/57 ,  H01L28/65

摘要： There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

公开(公告)号：US20050093042A1

公开(公告)日：2005-05-05

申请号：US10952871

申请日：2004-09-30

申请人： Keisuke Nakazawa ,  Hiroyuki Kanaya ,  Atsuko Kawasaki

发明人： Keisuke Nakazawa ,  Hiroyuki Kanaya ,  Atsuko Kawasaki

IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/312 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L21/02126 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L27/11507 ,  H01L28/57

摘要： A semiconductor device comprises a semiconductor substrate, a plurality of capacitors provided above the semiconductor substrate and including a lower electrode, a ferroelectric film, and an upper electrode, and a polysilazane-based coated insulating film provided on the plurality of capacitors and between the plurality of capacitors and burying a gap between the plurality of capacitors.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底之上并包括下电极，铁电体膜和上电极的多个电容器，以及设置在多个电容器上和多个电容器之间的聚硅氮烷基涂覆绝缘膜 的电容器并且掩埋多个电容器之间的间隙。

公开(公告)号：US20050070043A1

公开(公告)日：2005-03-31

申请号：US10673247

申请日：2003-09-30

申请人： Koji Yamakawa ,  Katsuaki Natori ,  Soichi Yamazaki ,  Osamu Arisumi ,  Hiroshi Itokawa ,  Hiroyuki Kanaya ,  Kazuhiro Tomioka ,  Keisuke Nakazawa ,  Yasuyuki Taniguchi ,  Uli Egger

发明人： Koji Yamakawa ,  Katsuaki Natori ,  Soichi Yamazaki ,  Osamu Arisumi ,  Hiroshi Itokawa ,  Hiroyuki Kanaya ,  Kazuhiro Tomioka ,  Keisuke Nakazawa ,  Yasuyuki Taniguchi ,  Uli Egger

IPC分类号： B23Q3/157 ,  H01L21/00 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L28/55 ,  H01L21/0332 ,  H01L21/31122 ,  H01L21/31144 ,  H01L28/65

摘要： The present invention provides a method for manufacturing a semiconductor device equipped with a capacitor in which a dielectric film is used, wherein a complex oxide is used as a mask material when the dielectric film is etched.

摘要翻译： 本发明提供了一种制造半导体器件的方法，所述半导体器件配备有使用电介质膜的电容器，其中当蚀刻所述电介质膜时，使用复合氧化物作为掩模材料。

公开(公告)号：US06699726B2

公开(公告)日：2004-03-02

申请号：US10336012

申请日：2003-01-03

申请人： Osamu Hidaka ,  Sumito Ootsuki ,  Hiroshi Mochizuki ,  Hiroyuki Kanaya ,  Kumi Okuwada ,  Tomio Katata ,  Norihisa Arai ,  Hiroyuki Takenaka

发明人： Osamu Hidaka ,  Sumito Ootsuki ,  Hiroshi Mochizuki ,  Hiroyuki Kanaya ,  Kumi Okuwada ,  Tomio Katata ,  Norihisa Arai ,  Hiroyuki Takenaka

IPC分类号： H01G706

CPC分类号： H01L21/76831 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76895 ,  H01L23/5226 ,  H01L27/11502 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film. One of the drain region and the source region and one of the upper electrode and the lower electrode of the capacitor are connected to each other by an electrode wiring. A wiring connected to the other one of the drain region and the source region is formed on the semiconductor substrate.

摘要翻译： 半导体器件以这样的方式构成，即在半导体衬底的表面层部分中形成具有由杂质扩散区域构成的漏极区域和源极区域的开关晶体管。 在含有晶体管的半导体基板上形成第一绝缘膜，在第一绝缘膜的上层侧形成电容器。 电容器包括下电极，包括铁电和高介电常数电介质之一的电极间绝缘膜和上电极。 在形成电极间绝缘膜之前，形成第二绝缘膜以覆盖电极间绝缘膜的侧面部分，第二绝缘膜保护电极间绝缘膜的侧面部分。 漏极区域和源极区域之一以及电容器的上部电极和下部电极中的一个通过电极布线彼此连接。 在半导体衬底上形成连接到另一个漏极区域和源极区域的布线。

公开(公告)号：US06611015B2

公开(公告)日：2003-08-26

申请号：US09956001

申请日：2001-09-20

申请人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

发明人： Tohru Ozaki ,  Iwao Kunishima ,  Toyota Morimoto ,  Hiroyuki Kanaya

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of the memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

摘要翻译： 一种半导体存储器件，包括具有形成在半导体衬底上的多个存储晶体管的存储单元块。 存储晶体管包括第一和第二杂质扩散区域以及在它们之间形成的栅极。 多个存储单元也包括在存储单元块中，并且具有连接到第一杂质扩散区的下电极，形成在下电极上的铁电膜和形成在铁电体膜上的第一上电极并连接到第二杂质扩散区 地区。 还包括形成在半导体衬底上并连接到存储单元块的一端的块选择晶体管。 第二上电极也形成为与块选择晶体管相邻并且与存储单元的第一上电极断开连接。

公开(公告)号：US06586790B2

公开(公告)日：2003-07-01

申请号：US09359324

申请日：1999-07-23

申请人： Hiroyuki Kanaya ,  Iwao Kunishima ,  Koji Yamakawa ,  Tsuyoshi Iwamoto ,  Hiroshi Mochizuki

发明人： Hiroyuki Kanaya ,  Iwao Kunishima ,  Koji Yamakawa ,  Tsuyoshi Iwamoto ,  Hiroshi Mochizuki

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/56 ,  H01L28/57 ,  H01L28/65

摘要： There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

摘要翻译： 提供一种半导体器件，其具有形成在被绝缘体膜覆盖的半导体衬底上的铁电电容器，其中所述强电介质电容器包括：形成在所述绝缘膜上的底部电极; 形成在底部电极上的铁电体膜; 以及形成在强电介质膜上的顶部电极。 铁电体膜具有两层铁电体膜或三层铁电体膜的层叠结构。 上部铁电膜被金属化，并防止氢在下部铁电层中扩散。 堆叠的铁电体膜的晶粒优选不同。

公开(公告)号：US06521927B2

公开(公告)日：2003-02-18

申请号：US09102616

申请日：1998-06-23

申请人： Osamu Hidaka ,  Sumito Ootsuki ,  Hiroshi Mochizuki ,  Hiroyuki Kanaya ,  Kumi Okuwada ,  Tomio Katata ,  Norihisa Arai ,  Hiroyuki Takenaka

发明人： Osamu Hidaka ,  Sumito Ootsuki ,  Hiroshi Mochizuki ,  Hiroyuki Kanaya ,  Kumi Okuwada ,  Tomio Katata ,  Norihisa Arai ,  Hiroyuki Takenaka

IPC分类号： H01L31119

CPC分类号： H01L21/76831 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76895 ,  H01L23/5226 ,  H01L27/11502 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film. One of the drain region and the source region and one of the upper electrode and the lower electrode of the capacitor are connected to each other by an electrode wiring. A wiring connected to the other one of the drain region and the source region is formed on the semiconductor. substrate.

摘要翻译： 半导体器件以这样的方式构成，即在半导体衬底的表面层部分中形成具有由杂质扩散区域构成的漏极区域和源极区域的开关晶体管。 在含有晶体管的半导体基板上形成第一绝缘膜，在第一绝缘膜的上层侧形成电容器。 电容器包括下电极，包括铁电和高介电常数电介质之一的电极间绝缘膜和上电极。 在形成电极间绝缘膜之前，形成第二绝缘膜以覆盖电极间绝缘膜的侧面部分，第二绝缘膜保护电极间绝缘膜的侧面部分。 漏极区域和源极区域之一以及电容器的上部电极和下部电极中的一个通过电极布线彼此连接。 在半导体上形成与漏极区域和源极区域中的另一个连接的布线。 基质。

公开(公告)号：US5757870A

公开(公告)日：1998-05-26

申请号：US517408

申请日：1995-08-21

申请人： Kazuyuki Miya ,  Roland Go ,  Hiroyuki Kanaya

发明人： Kazuyuki Miya ,  Roland Go ,  Hiroyuki Kanaya

IPC分类号： H04B1/707 ,  H04B1/7073 ,  H04B1/7075 ,  H04B7/26 ,  H04W56/00 ,  H04J13/04 ,  H04L7/02

CPC分类号： H04B1/70752 ,  H04B1/70754 ,  H04B1/70757

摘要： A synchronizing method and circuit accurately and stably operates a direct spread spectrum multiple access communication system. A signal transmitted by modulating the spreading code with data at the transmission side is sampled by a signal of n times (n: 1 or larger integer) the clock speed of the spread spectrum signal at the reception side, and the correlation is detected by a digital matched filter. Consequently, the detection output in every sample in the symbol period is compared with the envelope detection output determined in every sampling period, and the sample positions for a specific number of determined samples are stored in the descending order of the output. The number of times of storage of large sample positions in the stored detection output is counted in every symbol period, and the position of the largest number of storage times is detected as the peak position. From this peak position, capturing or holding the symbol period and setting of the reception window position results.

摘要翻译： 一种同步方法和电路准确稳定地操作直扩扩频多址通信系统。 通过在发送侧用数据调制扩展码发送的信号由接收侧的扩频信号的时钟速度的n倍（n = 1或更大整数）的信号进行采样，并且相关性由 数字匹配滤波器 因此，将符号周期中的每个采样中的检测输出与在每个采样周期中确定的包络检测输出进行比较，并且以输出的降序存储特定数量的确定采样的采样位置。 在每个符号周期中对存储的检测输出中的大样本位置的存储次数进行计数，并且检测最大数量的存储时间的位置作为峰值位置。 从该峰值位置，捕获或保持符号周期和接收窗口位置的设置结果。

公开(公告)号：US08969983B2

公开(公告)日：2015-03-03

申请号：US13425067

申请日：2012-03-20

申请人： Hiroyuki Kanaya

发明人： Hiroyuki Kanaya

IPC分类号： H01L29/82 ,  G11C11/00 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L21/00

CPC分类号： H01L43/12 ,  H01L27/226 ,  H01L27/228 ,  H01L43/08

摘要： A memory includes a semiconductor substrate. Cell transistors are on the substrate. Contact plugs each of which is buried between the adjacent cell transistors and electrically connected to a diffusion layer between the adjacent cell transistors. An interlayer dielectric film buries gaps between the contact plugs. A storage element is provided not above the contact plugs but above the interlayer dielectric film. A sidewall film covers a part of a side surface of the storage element, and is provided to overlap with one of the contact plugs as viewed from above a surface of the semiconductor substrate. A lower electrode is provided between a bottom of the storage element and the interlayer dielectric film and between the sidewall film and one of the contact plugs, and electrically connects the storage element to one of the contact plugs.

摘要翻译： 存储器包括半导体衬底。 单元晶体管在基板上。 接触插塞每个都埋在相邻的单元晶体管之间，并且电连接到相邻单元晶体管之间的扩散层。 层间电介质膜埋入接触插塞之间的间隙。 存储元件不设置在接触插塞上方，而是位于层间电介质膜之上。 侧壁膜覆盖存储元件的侧表面的一部分，并且设置成从半导体衬底的表面上方观察到与一个接触插塞重叠。 下部电极设置在存储元件的底部和层间电介质膜之间以及侧壁膜和其中一个接触插塞之间，并将存储元件电连接到一个接触插塞。

公开(公告)号：US20120193693A1

公开(公告)日：2012-08-02

申请号：US13235272

申请日：2011-09-16

申请人： Hiroyuki Kanaya

发明人： Hiroyuki Kanaya

IPC分类号： H01L27/22 ,  H01L43/12

CPC分类号： H01L27/228 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01L43/12

摘要： An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode.

摘要翻译： 本实施例的一个方面，提供了一种磁性随机存取存储器件，包括半导体衬底，半导体衬底上的选择晶体管，选择晶体管包括扩散层，扩散层上的接触插塞，接触插塞上的非晶膜 设置在非晶膜上的下电极，第一磁性层，非磁性层，第二磁性层，按顺序堆叠的上电极和接触插塞上的侧壁接触膜，所述侧壁接触膜与 上电极的侧壁。