公开(公告)号：US07768273B1

公开(公告)日：2010-08-03

申请号：US12396102

申请日：2009-03-02

申请人： Alexander Kalnitsky ,  Alan Kramer

发明人： Alexander Kalnitsky ,  Alan Kramer

IPC分类号： G01R27/26

CPC分类号： H01L27/0248 ,  G06K9/00053

摘要： A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes a first capacitor plate placed vertically under the upper surface of a dielectric layer and a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate. Electrostatic discharge protection relative to electrostatic potential that may be carried by an ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.

摘要翻译： 平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。 每个感测单元包括垂直于电介质层的上表面放置的第一电容器板和垂直于电介质层的上表面放置在与第一电容器板紧密的水平空间关系的第二电容器板。 通过在电介质层内放置多个接地的金属路径以空间地围绕第一和第二电容器板的每一个来提供相对于静电电位的静电放电保护，这是通过不接地的指尖承载的，这是以不是 打扰指尖的未接地状态。

公开(公告)号：US07700977B2

公开(公告)日：2010-04-20

申请号：US12037569

申请日：2008-02-26

申请人： Michael David Church ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

发明人： Michael David Church ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

IPC分类号： H01L23/62

CPC分类号： H01L27/0629 ,  H01L27/0255 ,  H01L27/0814

摘要： An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

摘要翻译： 集成电路包括并联连接的第一和第二二极管。 第一二极管具有第一击穿电压，并且在衬底的衬底的表面处具有彼此相邻的第一P型区域和第一N型区域，以形成横向二极管。 第二二极管具有小于第一击穿电压的第二击穿电压，并且在衬底中具有彼此相邻的第二P型区域和第二N型区域，以在表面下方形成横向二极管。第一和第二N型区域重叠 并且第一和第二P型区域电连接，由此第一和第二二极管是并联的。

公开(公告)号：US07522753B2

公开(公告)日：2009-04-21

申请号：US11162861

申请日：2005-09-27

申请人： Alexander Kalnitsky ,  Alan Kramer

发明人： Alexander Kalnitsky ,  Alan Kramer

IPC分类号： G06K9/00

CPC分类号： G06F3/044 ,  G06F2203/04107 ,  G06K9/00053 ,  H01L27/0248

摘要： A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input mode and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.

摘要翻译： 平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。 每个感测单元包括具有不接地输入模式的放大器和未接地输出节点。 通过以下步骤为每个放大器提供对指纹图案敏感的输出到输入负反馈：（1）第一电容器板，其垂直放置在电介质层的上表面下方并连接到未接地的放大器输入节点 ，（2）第二电容器板，其垂直于电介质层的上表面放置在与第一电容器板紧密的水平空间关系上，并连接到未接地的输出节点，（3）指纹图案为未接地的指尖 要被检测到，哪个未接地的指尖被放置在与第一和第二电容器板紧密垂直空间关系的电介质层的上表面上。 通过在电介质层内放置多个接地的金属路径来空间地围绕第一和第二电容器板中的每一个来提供相对于静电电位的静电放电保护，这是通过不接地的指尖来承载的， 打扰指尖的未接地状态。

公开(公告)号：US20080135968A1

公开(公告)日：2008-06-12

申请号：US11621443

申请日：2007-01-09

申请人： Alexander Kalnitsky ,  Dong Zheng ,  Joy Jones ,  Xijian Lin ,  Gregory Cestra

发明人： Alexander Kalnitsky ,  Dong Zheng ,  Joy Jones ,  Xijian Lin ,  Gregory Cestra

IPC分类号： H01L31/02

CPC分类号： H01L31/103 ,  H01L27/1443 ,  H01L31/02162

摘要： Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.

摘要翻译： 本发明的实施例涉及在抑制红外光的同时主要响应于可见光的光传感器。 这种传感器作为环境光传感器是特别有用的，因为这样的传感器可用于提供类似于人眼的光谱响应。 本发明的实施例还涉及提供这种光传感器的方法，以及使用这种光传感器的方法。

公开(公告)号：US20070247915A1

公开(公告)日：2007-10-25

申请号：US11498672

申请日：2006-08-02

申请人： Alexander Kalnitsky ,  Michael Church

发明人： Alexander Kalnitsky ,  Michael Church

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

公开(公告)号：US06855585B1

公开(公告)日：2005-02-15

申请号：US10002429

申请日：2001-10-31

申请人： Alexander Kalnitsky ,  Joseph Paul Elull ,  Ralph Wall ,  Robert F. Scheer ,  Jonathan Herman ,  Glenn Nobinger ,  Viktor Zekeriya

发明人： Alexander Kalnitsky ,  Joseph Paul Elull ,  Ralph Wall ,  Robert F. Scheer ,  Jonathan Herman ,  Glenn Nobinger ,  Viktor Zekeriya

IPC分类号： H01L27/01 ,  H01L27/08 ,  H01L21/302

CPC分类号： H01L27/0802 ,  H01L27/016

摘要： A method for forming multiple resistors on a substrate. The method initially includes providing a first resistor on the substrate. A first dielectric layer is deposited, patterned, and selectively etched over the first resistor. Second resistor material is provided over the first dielectric layer. Furthermore, landing pad material is provided over the second resistor material. The landing pad material and the second resistor material are then selectively etched. The selective etching forms contacts for the first resistor in a first region, and forms a second resistor and associated contacts in a second region.

摘要翻译： 一种在衬底上形成多个电阻器的方法。 该方法最初包括在衬底上提供第一电阻器。 在第一电阻器上沉积，图案化和选择性蚀刻第一电介质层。 第二电阻材料设置在第一介电层上。 此外，着陆垫材料设置在第二电阻材料上。 然后选择性地蚀刻着陆焊盘材料和第二电阻材料。 选择性蚀刻在第一区域中形成用于第一电阻器的触点，并且在第二区域中形成第二电阻器和相关联的触点。

公开(公告)号：US06686250B1

公开(公告)日：2004-02-03

申请号：US10300105

申请日：2002-11-20

申请人： Alexander Kalnitsky ,  Michael Rowlandson ,  Fanling H. Yang ,  Sang Park ,  Robert F. Scheer

发明人： Alexander Kalnitsky ,  Michael Rowlandson ,  Fanling H. Yang ,  Sang Park ,  Robert F. Scheer

IPC分类号： H01L21331

CPC分类号： H01L29/66287 ,  H01L29/66242

摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.

摘要翻译： 提供自对准双极晶体管及其形成方法。 双极晶体管具有由双层多晶硅形成的由y形结构表征的发射极区域。 双层多晶硅包括第一多晶硅发射极结构和第二多晶硅发射极结构。 形成双极晶体管的方法包括在衬底上形成发射极叠层。 发射极堆叠包括第一多晶硅发射极结构和插塞结构。 发射极堆叠将衬底限定为掩模部分并暴露于相邻部分。 暴露的相邻部分被选择性掺杂掺杂剂以限定非本征基区，其中掺杂剂被阻止进入掩蔽部分。 在选择性地掺杂非本征基极区域之后，将插塞结构从发射极堆叠移除，并且第二多晶硅发射极结构形成在第一多晶硅发射极结构上以限定双极晶体管的发射极区域。

公开(公告)号：US06525397B1

公开(公告)日：2003-02-25

申请号：US09376161

申请日：1999-08-17

申请人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

发明人： Alexander Kalnitsky ,  Pavel Poplevine ,  Albert Bergemont

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse. The transistor includes: a well region in a substrate, the well region forming the drain of the transistor; an insulating trench in the well; and a polysilicon gate extending over a portion of the substrate, a portion of the well and a portion of the trench, wherein upon reverse-biasing the junction between the well and the substrate a depletion region is formed which encompasses at least the entire portion of the surface region of the well over which the polysilicon extends.

摘要翻译： 集成的熔丝元件能够被编程为低电压工艺技术中的高电阻。 熔丝包括未掺杂的多晶硅层和硅化物层的堆叠。 施加在堆叠上的电压增加直到发生第一附聚事件，由此在硅化物层中形成不连续性。 电流进一步增加以引起第二聚集事件，从而增加不连续性的大小。 每个附聚事件会增加保险丝的电阻。 能够保持高电压的延伸漏极MOS晶体管与保险丝串联连接，以对熔丝进行编程。 晶体管包括：衬底中的阱区，形成晶体管的漏极的阱区; 井中的绝缘沟槽; 以及在所述衬底的一部分上延伸的多晶硅栅极，所述阱的一部分和所述沟槽的一部分，其中在反向偏置所述阱和所述衬底之间的结点时，形成耗尽区，所述耗尽区至少包括 多晶硅延伸的阱的表面区域。

公开(公告)号：US06368917B1

公开(公告)日：2002-04-09

申请号：US09721604

申请日：2000-11-21

申请人： Alexander Kalnitsky ,  Albert Bergemont

发明人： Alexander Kalnitsky ,  Albert Bergemont

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L27/11553

摘要： The present invention provides a method for forming a shaped floating gate on an integrated circuit substrate. A trench is etched in a surface of the integrated circuit substrate such that a tip is formed. The tip may be defined by a first sidewall that is approximately perpendicular to the surface of the integrated circuit substrate and a second sidewall that is disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is then formed over the substrate surface and conforming to the trench. Next, a conductive layer is deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. A bottom portion of the floating gate is then contained by the trench. The resulting floating gate and semiconductor device includes a dielectric layer disposed above an integrated circuit substrate surface. The substrate surface defines a trench having a tip that may be defined by a first sidewall and a second sidewall. A conductive layer is formed above the dielectric layer such that it fills the trench and defines a floating gate having a tip contained by the trench. In addition, a diffusion region may be disposed in the integrated circuit substrate such that the tip of the floating gate points into the diffusion region.

摘要翻译： 本发明提供一种在集成电路基板上形成成形浮栅的方法。 在集成电路基板的表面中蚀刻沟槽，从而形成尖端。 尖端可以由大致垂直于集成电路基板的表面的第一侧壁和与集成电路基板的表面成角度设置的第二侧壁限定。 然后在衬底表面上形成电介质层并且与沟槽一致。 接下来，在电介质层上方沉积导电层，使其填充沟槽。 然后蚀刻导电层，使得限定浮动栅极。 然后，浮动栅极的底部被沟槽包围。 所得的浮栅和半导体器件包括设置在集成电路衬底表面上方的电介质层。 衬底表面限定了具有可由第一侧壁和第二侧壁限定的尖端的沟槽。 导电层形成在电介质层之上，使得它填充沟槽并且限定具有由沟槽包含的尖端的浮动栅极。 此外，可以在集成电路基板中设置扩散区域，使得浮动栅极的尖端指向扩散区域。

公开(公告)号：US06365463B2

公开(公告)日：2002-04-02

申请号：US09316450

申请日：1999-05-21

申请人： Alexander Kalnitsky ,  Albert Bergemont

发明人： Alexander Kalnitsky ,  Albert Bergemont

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/82345

摘要： A process for forming high-precision analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up is disclosed. The process selectively implants the polysilicon layer that forms the gates of the analog transistors so that the doping concentration of the analog gates is greater than the doping concentration of the digital gates.

摘要翻译： 公开了一种用于形成具有低阈值电压卷积的高精度模拟晶体管和具有高阈值电压卷积的数字晶体管的工艺。 该过程选择性地植入形成模拟晶体管的栅极的多晶硅层，使得模拟栅极的掺杂浓度大于数字栅极的掺杂浓度。