公开(公告)号：US09129940B2

公开(公告)日：2015-09-08

申请号：US13419911

申请日：2012-03-14

申请人： Hsieh-Hung Hsieh ,  Yi-Hsuan Liu ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Yi-Hsuan Liu ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： G01R35/00 ,  H01L23/48 ,  H01L23/66 ,  H01L25/065 ,  H04B5/00

CPC分类号： H01L23/48 ,  H01L23/66 ,  H01L25/0657 ,  H01L2225/06531 ,  H01L2924/0002 ,  H04B5/0075 ,  H01L2924/00

摘要： An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.

摘要翻译： 集成电路包括在垂直堆叠中耦合到第一芯片的第一芯片和第二芯片。 第一芯片包括射频电路和电耦合到射频电路的第一线圈。 第二芯片包括校准电路和电耦合到校准电路的第二线圈。 校准电路被配置为通过第一和第二线圈之间的感应耦合来校准设置在第一芯片上的射频电路。

公开(公告)号：US08773866B2

公开(公告)日：2014-07-08

申请号：US12965402

申请日：2010-12-10

申请人： Jun-De Jin ,  Mei-Show Chen ,  Tzu-Jin Yeh

发明人： Jun-De Jin ,  Mei-Show Chen ,  Tzu-Jin Yeh

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： H01L23/645 ,  H01F19/04 ,  H01L23/48 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/14211 ,  H01L2924/14215 ,  H01L2924/1422 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107

摘要： A device includes an interposer and a radio-frequency (RF) device bonded to a first side of the interposer. The interposer includes a first side and a second side opposite to the first side. The interposer does not have through-interposer vias formed therein. First passive devices are formed on the first side of the interposer and electrically coupled to the RF device. Second passive devices are formed on the second side of the interposer. The first and the second passive devices are configured to transmit signals wirelessly between the first passive devices and the second passive devices.

摘要翻译： 一种装置包括插入器和结合到插入器的第一侧的射频（RF）装置。 插入器包括与第一侧相对的第一侧和第二侧。 插入件没有在其中形成通孔插入孔。 第一无源器件形成在插入器的第一侧上并电耦合到RF器件。 第二无源器件形成在插入器的第二侧上。 第一和第二无源器件被配置为在第一无源器件和第二无源器件之间无线地发送信号。

公开(公告)号：US20140036396A1

公开(公告)日：2014-02-06

申请号：US13562571

申请日：2012-07-31

申请人： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

发明人： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

IPC分类号： H02H9/04 ,  H05K13/00 ,  H03H7/01

CPC分类号： H03H7/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/64 ,  H01L2924/0002 ,  H02H9/04 ,  H02H9/046 ,  Y10T29/49117 ,  H01L2924/00

摘要： The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology.

摘要翻译： 本公开涉及可以重用于各种集成电路（IC）应用的片上静电放电（ESD）保护电路。 电感 - 电容（LC）并联谐振器和并联电感（连接到地）均用作ESD保护电路，也可用作给定IC应用的阻抗匹配网络的一部分。 ESD LC谐振器可以设计有各种带通滤波器（BPF）拓扑。 片上ESD保护电路允许同时优化ESD和BPF性能，用于集成无源器件（IPD）工艺的完全片上ESD解决方案，无需主动ESD器件保护，另外还支持片外ESD保护 保护，降低功耗，并创建可重用的BPF拓扑。

公开(公告)号：US08618631B2

公开(公告)日：2013-12-31

申请号：US13372873

申请日：2012-02-14

申请人： Jun-De Jin ,  Tzu-Jin Yeh

发明人： Jun-De Jin ,  Tzu-Jin Yeh

IPC分类号： H01L27/08 ,  H01L29/66 ,  H01L21/00

CPC分类号： H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

摘要翻译： 一种具有原位芯片级铁氧体磁珠电感器的半导体结构及其形成方法。 实施例包括基板，形成在基板上的第一介电层，形成在第一介电层上的下铁氧体层，以及与该结构中的下铁氧体层间隔开的上铁氧体层。 第一金属层可以形成在下铁素体层上方，第二金属层形成在上铁氧体层下面，其中至少第一或第二金属层具有包括多匝的线圈构型。 至少一个第二电介质层可以设置在第一和第二金属层之间。 铁氧体磁珠电感器具有小的外形尺寸，并且可以使用BEOL工艺来形成。

公开(公告)号：US20130181534A1

公开(公告)日：2013-07-18

申请号：US13350206

申请日：2012-01-13

申请人： Jun-De Jin ,  Tzu-Jin Yeh

发明人： Jun-De Jin ,  Tzu-Jin Yeh

IPC分类号： H01F38/14

CPC分类号： H01F38/14 ,  H01F27/2804 ,  H01F37/00 ,  H01L23/48 ,  H01L23/5227 ,  H01L23/64 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2225/06531

摘要： A transformer for RF and other frequency through-chip-interface (TCI) applications includes multiple chips in wireless electronic communication with one another in three-dimensional integrated circuit, 3DIC, technology. Each of the chips includes an inductor coil and a matching network that matches the impedance of the inductor coil. The matching network is electrically coupled between the inductor coil and further components and circuits formed on the chip.

摘要翻译： 用于RF和其他频率通过芯片接口（TCI）应用的变压器包括在三维集成电路，3DIC技术中彼此无线电子通信的多个芯片。 每个芯片包括电感线圈和与电感线圈的阻抗匹配的匹配网络。 匹配网络电耦合在电感线圈和形成在芯片上的其它部件和电路之间。

公开(公告)号：US20120286836A1

公开(公告)日：2012-11-15

申请号：US13103571

申请日：2011-05-09

申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03K3/84

CPC分类号： G01R31/2824

摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

公开(公告)号：US09397729B2

公开(公告)日：2016-07-19

申请号：US12946072

申请日：2010-11-15

申请人： Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H04B5/00

CPC分类号： H04B5/0081

摘要： Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.

摘要翻译： 芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。 第一线圈耦合到天线。 第二线圈耦合到放大器电路。 第二线圈不与第一线圈直接接触。 第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。

公开(公告)号：US09093977B2

公开(公告)日：2015-07-28

申请号：US13562571

申请日：2012-07-31

申请人： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

发明人： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

IPC分类号： H02H9/00 ,  H03H7/40 ,  H02H9/04 ,  H01L23/60 ,  H01L23/64 ,  H01L23/522

CPC分类号： H03H7/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/64 ,  H01L2924/0002 ,  H02H9/04 ,  H02H9/046 ,  Y10T29/49117 ,  H01L2924/00

摘要： The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology.

摘要翻译： 本公开涉及可以重用于各种集成电路（IC）应用的片上静电放电（ESD）保护电路。 电感 - 电容（LC）并联谐振器和并联电感（连接到地）均用作ESD保护电路，也可用作给定IC应用的阻抗匹配网络的一部分。 ESD LC谐振器可以设计有各种带通滤波器（BPF）拓扑。 片上ESD保护电路允许同时优化ESD和BPF性能，用于集成无源器件（IPD）工艺的完全片上ESD解决方案，无需主动ESD器件保护，另外还支持片外ESD保护 保护，降低功耗，并创建可重用的BPF拓扑。

公开(公告)号：US08729968B2

公开(公告)日：2014-05-20

申请号：US13103571

申请日：2011-05-09

申请人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03L5/00

CPC分类号： G01R31/2824

摘要： A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

摘要翻译： 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

公开(公告)号：US08664729B2

公开(公告)日：2014-03-04

申请号：US13325922

申请日：2011-12-14

申请人： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

发明人： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

IPC分类号： H01L27/088

CPC分类号： H01L29/66795 ,  H01L29/42372 ,  H01L29/785

摘要： Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.

摘要翻译： 降低栅极电阻finFET的方法和装置。 公开了一种金属栅极晶体管结构，其包括形成在半导体衬底上的多个半导体鳍片，所述鳍片平行布置并间隔开; 一个含金属的栅电极，形成在半导体衬底之上，并且覆盖每个半导体鳍片的沟道栅极区域，并且在半导体鳍片之间的半导体衬底上延伸; 覆盖所述栅电极和所述半导体衬底的层间电介质层; 以及多个触点，其布置在所述层间电介质层中并且延伸穿过所述层间电介质层到所述栅电极; 形成在所述层间电介质层上并且由所述多个触点耦合到所述栅电极的低电阻金属带; 其中所述多个触点与所述半导体鳍片的沟道栅极区域间隔开。 公开了形成栅极finFET的方法。