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45 条记录 (耗时 0.027 秒)

    System and method for modeling through silicon via
    21.
    发明授权
    System and method for modeling through silicon via 有权

    公开(公告)号：US09633149B2

    公开(公告)日：2017-04-25

    申请号：US13419959

    申请日：2012-03-14

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo

    IPC分类号： G06F9/455 ,  G06F17/50 ,  H01L23/498

    CPC分类号： G06F17/5036 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other.

    Apparatus and methods for de-embedding through substrate vias
    22.
    发明授权
    Apparatus and methods for de-embedding through substrate vias 有权
    用于通过衬底通孔去嵌入的装置和方法

    公开(公告)号：US08809073B2

    公开(公告)日：2014-08-19

    申请号：US13197602

    申请日：2011-08-03

    申请人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Victor Chih Yuan Chang ,  Min-Chie Jeng

    发明人： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Victor Chih Yuan Chang ,  Min-Chie Jeng

    IPC分类号： H01L21/66 ,  G01R31/26

    CPC分类号： G01R31/2644 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method includes providing on a substrate having at least two through substrate vias (“TSVs”) a plurality of test structures for de-embedding the measurement of the intrinsic characteristics of a device under test (DUT) including at least two of the TSVs; measuring the intrinsic characteristics [L] for a first and a second test structure on the substrate including two pads coupled with a transmission line of length L; using simultaneous solutions of ABCD matrix or T matrix form equations, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the pads and the transmission lines; de-embedding the measurements of the third and fourth test structures using the intrinsic characteristics of the pads and the transmission lines; and using simultaneous solutions of ABCD matrix or T matrix form equations for BM_L and BM_LX, and the measured intrinsic characteristics, solving for the intrinsic characteristics of the TSVs.

    摘要翻译： 一种方法包括在具有至少两个通过衬底通孔（“TSV”）的衬底上提供多个测试结构，用于对包括至少两个TSV的待测器件（DUT）的固有特性的测量进行解嵌入; 测量包括与长度为L的传输线耦合的两个焊盘的衬底上的第一和第二测试结构的固有特性[L] 使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解焊盘和传输线的固有特性; 使用焊盘和传输线的固有特性来解嵌第三和第四测试结构的测量; 并且对于BM_L和BM_LX使用ABCD矩阵或T矩阵形式方程的同时解，以及测量的固有特性，求解TSV的固有特性。

    Integrated circuit ground shielding structure
    25.
    发明授权
    Integrated circuit ground shielding structure 有权
    集成电路接地屏蔽结构

    公开(公告)号：US08659126B2

    公开(公告)日：2014-02-25

    申请号：US13313240

    申请日：2011-12-07

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    IPC分类号： H01L23/552

    CPC分类号： H01L23/5227 ,  H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

    摘要翻译： 本公开提供了一种集成电路（IC）装置。 IC器件包括包含电子元件的第一管芯。 IC器件包括包含接地屏蔽结构的第二管芯。 IC器件包括设置在第一管芯和第二管芯之间的层。 该层将第一管芯和第二管芯结合在一起。 本公开还涉及微电子器件。 微电子器件包括包含多个第一互连层的第一管芯。 电感线圈结构设置在第一互连层的子集中。 微电子器件包括包含多个第二互连层的第二管芯。 图案化接地屏蔽（PGS）结构设置在第二互连层的子集中。 微电子器件包括设置在第一和第二裸片之间的底部填充层。 底层填充层包含一个或多个微胶囊。

    INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE
    27.
    发明申请
    INTEGRATED CIRCUIT GROUND SHIELDING STRUCTURE 有权
    集成电路接地屏蔽结构

    公开(公告)号：US20130147023A1

    公开(公告)日：2013-06-13

    申请号：US13313240

    申请日：2011-12-07

    申请人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    发明人： Yu-Ling Lin ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou

    IPC分类号： H01L23/552

    CPC分类号： H01L23/5227 ,  H01L23/5225 ,  H01L23/552 ,  H01L23/585 ,  H01L23/645 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.

    摘要翻译： 本公开提供了一种集成电路（IC）装置。 IC器件包括包含电子元件的第一管芯。 IC器件包括包含接地屏蔽结构的第二管芯。 IC器件包括设置在第一管芯和第二管芯之间的层。 该层将第一管芯和第二管芯结合在一起。 本公开还涉及微电子器件。 微电子器件包括包含多个第一互连层的第一管芯。 电感线圈结构设置在第一互连层的子集中。 微电子器件包括包含多个第二互连层的第二管芯。 图案化接地屏蔽（PGS）结构设置在第二互连层的子集中。 微电子器件包括设置在第一和第二裸片之间的底部填充层。 底层填充层包含一个或多个微胶囊。