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41 条记录 (耗时 0.023 秒)

    Integrated circuits and methods of forming the same
    4.
    发明授权
    Integrated circuits and methods of forming the same 有权
    集成电路及其形成方法

    公开(公告)号：US08362591B2

    公开(公告)日：2013-01-29

    申请号：US12795734

    申请日：2010-06-08

    申请人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

    发明人： Hsiao-Tsung Yen ,  Hsien-Pin Hu ,  Jhe-Ching Lu ,  Chin-Wei Kuo ,  Ming-Fa Chen ,  Sally Liu

    IPC分类号： H01L29/93

    CPC分类号： H01L27/016 ,  H01L29/93

    摘要： A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

    摘要翻译： 三维集成电路包括半导体衬底，其中衬底具有延伸穿过衬底的第一表面和第二表面的开口，并且其中第一表面和第二表面是与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔（TSV）。 有源电路设置在衬底的第一表面上，电感器设置在衬底的第二表面上，并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管，使得导电材料邻近介电层设置，以及设置在TSV周围的杂质注入区域，使得介电层形成在 杂质注入区和TSV。

    DE-Embedding Method For On-Wafer Devices
    6.
    发明申请
    DE-Embedding Method For On-Wafer Devices 有权
    晶圆设备的嵌入方法

    公开(公告)号：US20090224791A1

    公开(公告)日：2009-09-10

    申请号：US12042606

    申请日：2008-03-05

    申请人： Hsiao-Tsung Yen ,  Tzu-Jin Yeh ,  Sally Liu

    发明人： Hsiao-Tsung Yen ,  Tzu-Jin Yeh ,  Sally Liu

    IPC分类号： G01R31/27

    CPC分类号： G01R31/2884 ,  H01L22/34

    摘要： A method and system for de-embedding an on-wafer device is disclosed. The method comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).

    摘要翻译： 公开了一种用于去嵌入晶片装置的方法和系统。 该方法包括使用一组ABCD矩阵分量表示测试结构的固有特性; 确定测试结构产生的内在特性; 并且使用确定的测试结构的固有特性来产生表示待测器件（“DUT”）的固有特性的一组参数。

    Method and apparatus for de-embedding on-wafer devices
    7.
    发明授权
    Method and apparatus for de-embedding on-wafer devices 有权
    用于去嵌入晶片装置的方法和装置

    公开(公告)号：US07954080B2

    公开(公告)日：2011-05-31

    申请号：US12042606

    申请日：2008-03-05

    申请人： Hsiao-Tsung Yen ,  Tzu-Jin Yeh ,  Sally Liu

    发明人： Hsiao-Tsung Yen ,  Tzu-Jin Yeh ,  Sally Liu

    IPC分类号： G06F17/50

    CPC分类号： G01R31/2884 ,  H01L22/34

    摘要： A method and system for de-embedding an on-wafer device is disclosed. The method comprises representing the intrinsic characteristics of a test structure using a set of ABCD matrix components; determining the intrinsic characteristics arising from the test structure; and using the determined intrinsic characteristics of the test structure to produce a set of parameters representative of the intrinsic characteristics of a device-under-test (“DUT”).

    摘要翻译： 公开了一种用于去嵌入晶片装置的方法和系统。 该方法包括使用一组ABCD矩阵分量表示测试结构的固有特性; 确定测试结构产生的内在特性; 并且使用确定的测试结构的固有特性来产生表示待测器件（“DUT”）的固有特性的一组参数。

    Balun system and method
    8.
    发明授权
    Balun system and method 有权
    巴伦系统和方法

    公开(公告)号：US08502620B2

    公开(公告)日：2013-08-06

    申请号：US12944847

    申请日：2010-11-12

    申请人： Jhe-Ching Lu ,  Hsiao-Tsung Yen ,  Sally Liu ,  Tzu-Jin Yeh ,  Min-Chie Jeng

    发明人： Jhe-Ching Lu ,  Hsiao-Tsung Yen ,  Sally Liu ,  Tzu-Jin Yeh ,  Min-Chie Jeng

    IPC分类号： H01P5/10 ,  H01P3/08

    CPC分类号： H01F21/12 ,  H01F27/2804 ,  H01F2027/2809 ,  H03H7/42 ,  Y10T29/49117

    摘要： A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers.

    摘要翻译： 公开了一种用于发送信号的系统和方法。 一个实施例包括一个平衡 - 不平衡变换器，例如Marchand平衡 - 不平衡转换器，其具有带初级线圈的第一变压器和第一次级线圈，以及具有初级线圈的第二变压器和第二次级线圈。 第一次级线圈和第二次级线圈连接到接地平面，并且接地平面具有位于第一变压器和第二变压器中的线圈分离下方的槽线。 缝线也可以具有手指。

    Balun System and Method
    9.
    发明申请
    Balun System and Method 有权
    巴伦系统和方法

    公开(公告)号：US20120119845A1

    公开(公告)日：2012-05-17

    申请号：US12944847

    申请日：2010-11-12

    申请人： Jhe-Ching Lu ,  Hsiao-Tsung Yen ,  Sally Liu ,  Tzu-Jin Yeh ,  Min-Chie Jeng

    发明人： Jhe-Ching Lu ,  Hsiao-Tsung Yen ,  Sally Liu ,  Tzu-Jin Yeh ,  Min-Chie Jeng

    IPC分类号： H01P5/10 ,  H05K13/00 ,  H01F27/29 ,  H01F38/00

    CPC分类号： H01F21/12 ,  H01F27/2804 ,  H01F2027/2809 ,  H03H7/42 ,  Y10T29/49117

    摘要： A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers.

    摘要翻译： 公开了一种用于发送信号的系统和方法。 一个实施例包括一个平衡 - 不平衡变换器，例如Marchand平衡 - 不平衡转换器，其具有带初级线圈的第一变压器和第一次级线圈，以及具有初级线圈的第二变压器和第二次级线圈。 第一次级线圈和第二次级线圈连接到接地平面，并且接地平面具有位于第一变压器和第二变压器中的线圈分离下方的槽线。 缝线也可以具有手指。

    Gated-varactors
    10.
    发明授权
    Gated-varactors 有权
    门控变容二极管

    公开(公告)号：US08609479B2

    公开(公告)日：2013-12-17

    申请号：US13595667

    申请日：2012-08-27

    申请人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin Wei Kuo ,  Sally Liu

    发明人： Chia-Chung Chen ,  Chewn-Pu Jou ,  Chin Wei Kuo ,  Sally Liu

    IPC分类号： H01L21/02

    CPC分类号： H01L29/93 ,  H01L29/7391 ,  H01L29/94

    摘要： In at least one embodiment, a method of manufacturing a varactor includes forming a well over a substrate. The well has a first type doping. A first source region and a second source region are formed in the well, and the first source region and the second source region have a second type doping. A drain region is formed in the well, and the drain region has the first type doping. A first gate region is formed over the well between the drain region and the first source region. Moreover, a second gate region is formed over the well between the drain region and the second source region.

    摘要翻译： 在至少一个实施例中，制造变容二极管的方法包括在衬底上形成阱。 该井具有第一种掺杂。 在阱中形成第一源极区域和第二源极区域，并且第一源极区域和第二源极区域具有第二类型掺杂。 在阱中形成漏极区，漏区具有第一类掺杂。 在漏极区域和第一源极区域之间的阱上形成第一栅极区域。 此外，在漏极区域和第二源极区域之间的阱之上形成第二栅极区域。