公开(公告)号：US20180166558A1

公开(公告)日：2018-06-14

申请号：US15822497

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Liesbeth Witters ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/66553 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

公开(公告)号：US09972622B2

公开(公告)日：2018-05-15

申请号：US15152700

申请日：2016-05-12

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Anabela Veloso

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/7848

Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.

公开(公告)号：US20140377936A1

公开(公告)日：2014-12-25

申请号：US14313928

申请日：2014-06-24

Applicant: IMEC VZW ,  Samsung Electronics Co. Ltd.

Inventor： Seung Hun Lee ,  Liesbeth Witters ,  Roger Loo

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02658 ,  H01L21/02587 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/1054

Abstract: The present disclosure relates to a method for forming a strained semiconductor structure. The method comprises providing a strain relaxed buffer layer, forming a sacrificial layer on the strain relaxed buffer layer, forming a shallow trench isolation structure through the sacrificial layer, removing at least a portion of an oxide layer on the sacrificial layer, etching through the sacrificial layer such that a portion of the strain relaxed buffer layer is exposed, forming the strained semiconductor structure on the exposed portion of the strain relaxed buffer layer.

Abstract translation: 本发明涉及形成应变半导体结构的方法。 该方法包括提供应变松弛缓冲层，在应变松弛缓冲层上形成牺牲层，通过牺牲层形成浅沟槽隔离结构，去除牺牲层上的氧化物层的至少一部分，蚀刻通过牺牲层 使得应变松弛缓冲层的一部分被暴露，在应变松弛缓冲层的暴露部分上形成应变半导体结构。

公开(公告)号：US20250118564A1

公开(公告)日：2025-04-10

申请号：US18906945

申请日：2024-10-04

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Liesbeth Witters

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/768

Abstract: A layer of semiconductor devices is produced on the frontside of a crystalline semiconductor substrate, in regions separated by dielectric-filled cavities formed previously. Additional layers are then formed on the device layer. The substrate is then flipped and bonded face down to a second substrate, following by the thinning of the crystalline first substrate from the backside. The thinning proceeds as far as possible without removing the full thickness of the first substrate anywhere across its surface. After this, an anisotropic etch is performed to remove additional material of the first substrate. The in-plane dimensions of the device regions separated by the dielectric-filled cavities are specified so that the anisotropic etch is stopped by a crystallographic plane of the substrate material or by the dielectric material in the cavities, before it can reach the devices on the frontside.

公开(公告)号：US20210358748A1

公开(公告)日：2021-11-18

申请号：US17323540

申请日：2021-05-18

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Niamh Waldron ,  Amey Mahadev Walke ,  Bernardette Kunert ,  Yves Mols

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/778 ,  H01L29/66

Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.

公开(公告)号：US10361268B2

公开(公告)日：2019-07-23

申请号：US15907878

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

IPC: H01L29/06 ,  H01L29/66 ,  B82Y40/00 ,  H01L21/8234 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L21/311

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

公开(公告)号：US10269929B2

公开(公告)日：2019-04-23

申请号：US15822497

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Liesbeth Witters ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to a method of forming an internal spacer between nanowires in a semiconductor device. The method includes providing a semiconductor structure comprising at least one fin. The at least one fin is comprised of a stack of layers of sacrificial material alternated with layers of nanowire material. The semiconductor structure is comprised of a dummy gate which partly covers the stack of layers of the at least one fin. The method also includes removing at least the sacrificial material next to the dummy gate and oxidizing the sacrificial material and the nanowire material next to the dummy gate. This removal results, respectively, in a spacer oxide and in a nanowire oxide. Additionally, the method includes removing the nanowire oxide until at least a part of the spacer oxide is remaining, wherein the remaining spacer oxide is the internal spacer.

公开(公告)号：US20180254321A1

公开(公告)日：2018-09-06

申请号：US15907878

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L29/0653 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823425 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

公开(公告)号：US09842777B2

公开(公告)日：2017-12-12

申请号：US15199535

申请日：2016-06-30

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Kurt Wostyn

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/16 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3065 ,  H01L21/823412 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7849 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks. The method further includes selectively removing the second layer from each of the layer stacks with respect to the third layer, wherein removing the second layer comprises at least partially removing the second layer through the gap, thereby defining the channels comprising a plurality of vertically arranged third layers.

公开(公告)号：US09502415B2

公开(公告)日：2016-11-22

申请号：US14808459

申请日：2015-07-24

Applicant: IMEC VZW

Inventor： Roger Loo ,  Jerome Mitard ,  Liesbeth Witters

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02645 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer. The properties of the first seed layer and the common strained relaxed buffer layer are predetermined such that the common channel layer is under a tensile strain or is unstrained in the nMOS region and is under a compressive strain in the pMOS region. Aspects also include devices formed using the method.

Abstract translation: 所公开的技术通常涉及互补金属氧化物 - 硅（CMOS）器件，更具体地涉及n沟道金属氧化物硅（nMOS）器件和p沟道金属氧化物（pMOS）器件，其是 在不同类型的菌株下。 在一个方面，一种方法包括在半导体衬底上的电介质层中提供沟槽，其中至少第一沟槽限定nMOS区域，并且第二沟槽限定pMOS区域，并且其中沟槽延伸穿过介电层并邻接表面 的基底。 该方法还包括在表面上的第一沟槽中生长第一籽晶层，并在第一沟槽和第二沟槽中生长共同的应变松弛缓冲层，其中常见的应变松弛缓冲层包括硅锗（SiGe）。 该方法还包括在第一和第二沟槽中以及共同的应变松弛缓冲层上生长包括锗（Ge）的公共沟道层。 第一种子层和公共应变松弛缓冲层的性质是预定的，使得公共沟道层处于拉伸应变或在nMOS区域中不受约束，并且在pMOS区域中具有压缩应变。 方面还包括使用该方法形成的装置。