公开(公告)号：US10720363B2

公开(公告)日：2020-07-21

申请号：US15977381

申请日：2018-05-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/306 ,  H01L29/78 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L21/308 ,  H01L29/66 ,  H01L29/786

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.

公开(公告)号：US10607896B2

公开(公告)日：2020-03-31

申请号：US15591944

申请日：2017-05-10

Applicant: IMEC VZW

Inventor： Lars-Ake Ragnarsson ,  Hendrik F.W. Dekkers ,  Tom Schram ,  Julien Ryckaert ,  Naoto Horiguchi ,  Mustafa Badaroglu

IPC: H01L21/8238 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L21/02

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.

公开(公告)号：US10522552B2

公开(公告)日：2019-12-31

申请号：US15980604

申请日：2018-05-15

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device. The dielectric on the sidewalls of the first and third layers electrically isolates the source and drain regions from the gate contacting layer.

公开(公告)号：US10439036B2

公开(公告)日：2019-10-08

申请号：US15374886

申请日：2016-12-09

Applicant: IMEC VZW

Inventor： Alessio Spessot ,  An De Keersgieter ,  Naoto Horiguchi

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265 ,  H01L29/49

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices such as metal-oxide-semiconductor (MOS) transistor devices. In one aspect, a transistor device comprises a channel region in a substrate partially delimited by a source and a drain junction at a main surface of the substrate. A first dielectric layer stack is arranged on the channel region, such that an orthogonal projection of the first dielectric layer stack on the main surface defining a first area is between and does not overlap the junctions and. A second dielectric layer stack is formed laterally adjacent to and in contact with the first dielectric layer stack, such that an orthogonal projection of the second dielectric layer stack overlaps the junction and defines a second area. A metal gate layer is formed on the first and second dielectric layer stacks, where an orthogonal projection of the metal gate layer on the main surface overlaps the first area and the second area. The first dielectric layer stack has a larger capacitance than the second dielectric layer stack.

公开(公告)号：US20170330801A1

公开(公告)日：2017-11-16

申请号：US15591944

申请日：2017-05-10

Applicant: IMEC VZW

Inventor： Lars-Ake Ragnarsson ,  Hendrik F.W. Dekkers ,  Tom Schram ,  Julien Ryckaert ,  Naoto Horiguchi ,  Mustafa Badaroglu

IPC: H01L21/8238 ,  H01L21/02

CPC classification number: H01L21/823857 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66545

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.

公开(公告)号：US20170170289A1

公开(公告)日：2017-06-15

申请号：US15374886

申请日：2016-12-09

Applicant: IMEC VZW

Inventor： Alessio Spessot ,  An De Keersgieter ,  Naoto Horiguchi

IPC: H01L29/51 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/512 ,  H01L21/265 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices such as metal-oxide-semiconductor (MOS) transistor devices. In one aspect, a transistor device comprises a channel region in a substrate partially delimited by a source and a drain junction at a main surface of the substrate. A first dielectric layer stack is arranged on the channel region, such that an orthogonal projection of the first dielectric layer stack on the main surface defining a first area is between and does not overlap the junctions and. A second dielectric layer stack is formed laterally adjacent to and in contact with the first dielectric layer stack, such that an orthogonal projection of the second dielectric layer stack overlaps the junction and defines a second area. A metal gate layer is formed on the first and second dielectric layer stacks, where an orthogonal projection of the metal gate layer on the main surface overlaps the first area and the second area. The first dielectric layer stack has a larger capacitance than the second dielectric layer stack

公开(公告)号：US20240234207A9

公开(公告)日：2024-07-11

申请号：US18486370

申请日：2023-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

公开(公告)号：US20230178630A1

公开(公告)日：2023-06-08

申请号：US18061065

申请日：2022-12-02

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Naoto Horiguchi ,  Julien Ryckaert

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

CPC classification number: H01L29/66439 ,  H01L21/266 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545

Abstract: A method for forming a FET device is provided. The method includes: forming a fin structure comprising a layer stack comprising channel layers and non-channel layers alternating the channel layers; etching each of first and second fin parts from each of first and second opposite sides of the fin structure such that a set of source cavities extending through the first fin part is formed in a first set of layers of the layer stack, and such that a set of drain cavities extending through the second fin part is formed in the first set of layers of the layer stack; filling the source and drain cavities with a dummy material; while masking the fin structure from the second side: removing the dummy material by etching from the first side, and subsequently, forming a source body and a drain body, each comprising a respective common body portion and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively; and while masking the fin structure from the first side: etching a third fin part from the second side such that a set of gate cavities extending through the third fin part is formed in a second set of layers, and subsequently, forming a gate body comprising a common gate body portion and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US11515399B2

公开(公告)日：2022-11-29

申请号：US17112844

申请日：2020-12-04

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L21/02 ,  H01L21/8238

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure. Further, the method can comprise etching back the contact material layer below a top surface of the first dielectric wall, thereby forming a first contact contacting the first source/drain portion of the first transistor structure, and a second contact contacting the first source/drain portion of the second transistor structure.

公开(公告)号：US11367662B2

公开(公告)日：2022-06-21

申请号：US16938168

申请日：2020-07-24

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Yusuke Oniki ,  Lars-Ake Ragnarsson ,  Naoto Horiguchi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66

Abstract: The disclosed technology generally relates to semiconductor devices and methods of forming the same. In one aspect, a method of forming a semiconductor device having a first field-effect transistor (FET) device and a second FET device comprises forming the first and second FET devices from a first stack and a second stack comprising a channel material arranged on a sacrificial material. The method can include forming first spacers at sidewalls of the first and second stacks, and forming a second spacer between the first spacers. After recessing of the sacrificial material and removal of the first spacers, gate structures may be formed, wrapping around the at least partly released channel portions. The gate structure of the first transistor device can be separated from the gate structure of the second transistor device by the second spacer.