公开(公告)号：US12211824B2

公开(公告)日：2025-01-28

申请号：US18130952

申请日：2023-04-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bäßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

公开(公告)号：US20230361087A1

公开(公告)日：2023-11-09

申请号：US17736519

申请日：2022-05-04

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Baessler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/498 ,  H01L23/495

CPC classification number: H01L25/072 ,  H01L23/49811 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/49833 ,  H01L23/4952 ,  H01L23/3121

Abstract: A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.

公开(公告)号：US20220285178A1

公开(公告)日：2022-09-08

申请号：US17685870

申请日：2022-03-03

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann

IPC: H01L21/67 ,  H01L21/56

Abstract: A device for forming a housing for a power semiconductor module arrangement includes a mold. The mold includes a first cavity including a plurality of first openings and a second opening, the second opening being coupled to a runner system, wherein the runner system is configured to inject a mold material into the first cavity through the second opening. The device further includes a plurality of sleeves or hollow bushings, wherein a first end of each of the plurality of sleeves or hollow bushings is arranged in one of the first openings, and wherein a second end of each of the plurality of sleeves or hollow bushings extends to the outside of the mold, a heating element configured to heat the mold, and a cooling element configured to cool the plurality of sleeves or hollow bushings.

公开(公告)号：US11264356B2

公开(公告)日：2022-03-01

申请号：US16842417

申请日：2020-04-07

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Andreas Grassmann ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.

公开(公告)号：US10211133B2

公开(公告)日：2019-02-19

申请号：US15810733

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Angela Kessler ,  Ivan Nikitin

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/00 ,  H01L23/373 ,  H01L23/433

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

公开(公告)号：US20180138111A1

公开(公告)日：2018-05-17

申请号：US15810733

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Juergen Hoegerl ,  Angela Kessler ,  Ivan Nikitin

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4882 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/83906 ,  H01L2924/014

Abstract: A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

公开(公告)号：US09934990B2

公开(公告)日：2018-04-03

申请号：US15420321

申请日：2017-01-31

Applicant: Infineon Technologies AG

Inventor： Inpil Yoo ,  Andreas Grassmann

IPC: H01L21/48 ,  H01L23/473 ,  H01L23/498 ,  H01L23/18 ,  H01L21/54 ,  H01L23/373 ,  H01L23/44 ,  H01L21/56 ,  H01L23/08 ,  H01L23/367 ,  H01L23/31

CPC classification number: H01L21/4882 ,  H01L21/4817 ,  H01L21/4875 ,  H01L21/54 ,  H01L21/565 ,  H01L23/08 ,  H01L23/18 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/3672 ,  H01L23/3737 ,  H01L23/44 ,  H01L23/473 ,  H01L23/49811

Abstract: A cooling apparatus is manufactured by: receiving a discrete module by a first singular part, the discrete module including a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and protruding out of the mold compound, and a first cooling plate at least partly uncovered by the mold compound; attaching a second singular part to a periphery of the first part to form a housing, the housing surrounding a periphery of the discrete module, the second part having a cutout which exposes the first cooling plate and a sealing structure facing a side of the discrete module with the first cooling plate; and filling the sealing structure with a sealing material which forms a water-tight seal around the periphery of the discrete module at the side of the discrete module with the first cooling plate.

公开(公告)号：US20160293524A1

公开(公告)日：2016-10-06

申请号：US15082387

申请日：2016-03-28

Applicant: Infineon Technologies AG

Inventor： Andreas Grassmann ,  Juergen Hoegerl

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/3114 ,  H01L23/3121 ,  H01L23/49517 ,  H01L23/49562 ,  H01L23/49844

Abstract: An electronic module includes a circuit board, having a carrier layer, the carrier layer having a plurality of recess areas in a main surface thereof, and a plurality of electronic sub-modules, each one of the sub-modules being disposed in one of the recess areas and each one of the sub-modules having a carrier, a semiconductor chip disposed on the carrier, and an encapsulation material disposed on the carrier and on the semiconductor chip.

Abstract translation: 电子模块包括具有载体层的电路板，载体层在其主表面上具有多个凹陷区域，以及多个电子子模块，每个子模块设置在 凹部区域，并且每个子模块具有载体，设置在载体上的半导体芯片，以及设置在载体上和半导体芯片上的封装材料。

公开(公告)号：US20140353818A1

公开(公告)日：2014-12-04

申请号：US13909133

申请日：2013-06-04

Applicant: Infineon Technologies AG

Inventor： Ottmar GEITNER ,  Wolfram HABLE ,  Andreas Grassmann ,  Frank Winter ,  Christian Neugirg ,  Ivan Nikitin

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/89 ,  H01L23/3107 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/26135 ,  H01L2224/29005 ,  H01L2224/291 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/30181 ,  H01L2224/83048 ,  H01L2224/83139 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/97 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer

Abstract translation: 提供一种制造包括两个基板的功率模块的方法，其中所述方法包括在第一基板之上设置第一厚度的补偿层; 在补偿层之上设置第二衬底; 以及在所述第二衬底设置在所述补偿层上之后，将所述补偿层的厚度从所述第一厚度减小到第二厚度

公开(公告)号：US20250054843A1

公开(公告)日：2025-02-13

申请号：US18931698

申请日：2024-10-30

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Marcus Böhm ,  Andreas Grassmann ,  Martin Gruber ,  Uwe Schindler

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.