公开(公告)号：US20160005686A1

公开(公告)日：2016-01-07

申请号：US14856967

申请日：2015-09-17

Applicant: International Business Machines Corporation

Inventor： Roy R. YU ,  Wilfried HAENSCH

IPC: H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: B32B37/02 ,  B32B37/12 ,  B32B38/1841 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/14 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/09 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/16147 ,  H01L2224/26135 ,  H01L2224/291 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00

Abstract: A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory.

Abstract translation: 4D设备包括2D多核逻辑和通过存储器堆叠侧壁使用细间距T＆J连接连接的3D存储器堆栈。 堆叠中的3D存储器从原始晶片厚度减薄到不剩余的Si。 存储晶圆顶部和底部表面的凹槽和凹槽装置允许精确的堆叠对准。 存储器堆栈还在背面具有微通道以允许流体冷却。 存储器堆栈以固定的时钟周期距离进一步切割，并在其侧面翻转并且重新组装到模板上成为伪晶片格式。 组件的顶侧壁被抛光并用BEOL构建以扇出，并且使用T＆J细间距连接来连接到2D逻辑晶片。 存储器堆叠的另一面被抛光，扇形，并用C4焊料撞击。 本发明还包括一种制造该装置的方法。 另一方面，本发明包括一个4D处理和器件，每个芯片超过50×大于2D存储密度和超高密度存储器。

公开(公告)号：US20120319261A1

公开(公告)日：2012-12-20

申请号：US13163935

申请日：2011-06-20

Applicant: Cody B. Moody

Inventor： Cody B. Moody

IPC: H01L23/02 ,  H01L21/50

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L23/10 ,  H01L24/03 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/26135 ,  H01L2224/29023 ,  H01L2224/29035 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29609 ,  H01L2224/29611 ,  H01L2224/29624 ,  H01L2224/29644 ,  H01L2224/29686 ,  H01L2224/32055 ,  H01L2224/32148 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83054 ,  H01L2224/8309 ,  H01L2224/83139 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/83825 ,  H01L2224/83948 ,  H01L2224/94 ,  H01L2924/01032 ,  H01L2924/01322 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Hermetically sealed semiconductor wafer packages that include a first bond ring on a first wafer facing a complementary surface of a second bond ring on a second wafer. The package includes first and second standoffs of a first material, having a first thickness, formed on a surface of the first bond ring. The package also includes a eutectic alloy (does not have to be eutectic, typically it will be an alloy not specific to the eutectic ratio of the elements) formed from a second material and the first material to create a hermetic seal between the first and second wafer, the eutectic alloy formed by heating the first and second wafers to a temperature above a reflow temperature of the second material and below a reflow temperature of the first material, wherein the eutectic alloy fills a volume between the first and second standoffs and the first and second bond rings, and wherein the standoffs maintain a prespecified distance between the first bond ring and the second bond ring.

Abstract translation: 密封的半导体晶片封装，其包括在第一晶片上的第一结合环，其面向第二晶片上的第二结合环的互补表面。 该封装包括形成在第一结合环的表面上的第一材料的第一和第二间隔，第一和第二间隔具有第一厚度。 该封装还包括共晶合金（不一定是共晶的，通常它是一种不是特定于元素的共晶比的合金），由第二种材料形成，并且第一种材料在第一和第二种之间形成气密封 晶片，通过将第一和第二晶片加热到高于第二材料的回流温度并低于第一材料的回流温度的温度而形成的共晶合金，其中共晶合金填充第一和第二间隙之间的体积， 和第二结合环，并且其中所述支架在所述第一结合环和所述第二结合环之间保持预定的距离。

公开(公告)号：US20110103034A1

公开(公告)日：2011-05-05

申请号：US12939747

申请日：2010-11-04

Applicant: Yao-Sheng Huang ,  Ching-Jung Yang

Inventor： Yao-Sheng Huang ,  Ching-Jung Yang

IPC: H05K7/00

CPC classification number: H05K3/323 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/83 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/16225 ,  H01L2224/26122 ,  H01L2224/26135 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/83101 ,  H01L2224/83139 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10157 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  H01L2924/00

Abstract: An electronic chip includes a plurality of conducting pins and a plurality of insulating blocks. The conducting pins are disposed on an outer side of the electronic chip to provide electrical connections between the electronic chip and an external circuit. Each of the insulating blocks is disposed between two adjacent conducting pins.

Abstract translation: 电子芯片包括多个导电引脚和多个绝缘块。 导电引脚设置在电子芯片的外侧，以提供电子芯片和外部电路之间的电连接。 每个绝缘块设置在两个相邻的导电销之间。

公开(公告)号：US09401349B2

公开(公告)日：2016-07-26

申请号：US14723893

申请日：2015-05-28

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Malta) Ltd ,  STMicroelectronics S.r.l.

Inventor： Angelo Crobu ,  Kenneth Fonk ,  Romain Coffy

IPC: G01P15/08 ,  H01L25/18 ,  G01L19/14 ,  H01L23/24 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/18 ,  G01L19/0084 ,  G01L19/147 ,  G01L19/148 ,  H01L23/24 ,  H01L23/3157 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1319 ,  H01L2224/16145 ,  H01L2224/26122 ,  H01L2224/26135 ,  H01L2224/29007 ,  H01L2224/29021 ,  H01L2224/29036 ,  H01L2224/32014 ,  H01L2224/32111 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/16151 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A stack of chips is formed by a first integrated-circuit chip and a second integrated-circuit chip. The chips have opposing faces which are separated from each other by an interposed spacer. The spacer is fastened by adhesion to only one of the opposing faces. The opposing faces are fastened to each other by a local adhesive which is separate from spacer.

Abstract translation: 一堆芯片由第一集成电路芯片和第二集成电路芯片形成。 芯片具有通过插入的间隔件彼此分离的相对面。 间隔件通过粘合固定到只有一个相对的面。 相对的面通过与间隔物分离的局部粘合剂彼此紧固。

公开(公告)号：US09259902B2

公开(公告)日：2016-02-16

申请号：US13353183

申请日：2012-01-18

Applicant: Roy R. Yu ,  Wilfried Haensch

Inventor： Roy R. Yu ,  Wilfried Haensch

IPC: H01L21/98 ,  B32B37/02 ,  H01L23/473 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  B32B37/12 ,  B32B38/18 ,  H01L29/06

CPC classification number: B32B37/02 ,  B32B37/12 ,  B32B38/1841 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/14 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/09 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/16147 ,  H01L2224/26135 ,  H01L2224/291 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00

Abstract: A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling, and is further diced at the fixed clock-cycle distance, and flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.

Abstract translation: 4D设备包括2D多核逻辑和通过存储器堆叠侧壁使用细间距T＆J连接连接的3D存储器堆栈。 堆叠中的3D存储器从原始晶片厚度减薄到没有剩余的Si。 存储晶片顶部和底部表面上的舌形槽装置允许精确的堆叠对准。 存储器堆栈还在背面具有微通道以允许流体冷却，并且以固定的时钟周期距离进一步切割，并在其侧面翻转并且重新组装到模板上成为伪晶片格式。 组件的顶侧壁被抛光并用BEOL构建以扇出，并且使用T＆J细间距连接来连接到2D逻辑晶片。 存储器堆叠的另一面被抛光，扇形，并用C4焊料撞击。 本发明还包括一种制造该装置的方法。

公开(公告)号：US20150130056A1

公开(公告)日：2015-05-14

申请号：US14600371

申请日：2015-01-20

Applicant: Sony Corporation

Inventor： Satoru Wakiyama

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11015 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/26135 ,  H01L2224/26145 ,  H01L2224/26165 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48 ,  H01L2224/73104 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83007 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract translation: 一种包括半导体元件的半导体器件; 形成在半导体元件上的焊盘电极; 形成在半导体元件上的对准标记; 形成在焊盘电极上的连接电极; 以及形成为覆盖连接电极的底部填充树脂。 来自半导体元件的对准标记的高度大于连接电极的高度。

公开(公告)号：US08962440B2

公开(公告)日：2015-02-24

申请号：US14462776

申请日：2014-08-19

Applicant: Sony Corporation

Inventor： Satoru Wakiyama

IPC: H01L21/20 ,  H01L21/56 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11015 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/26135 ,  H01L2224/26145 ,  H01L2224/26165 ,  H01L2224/27334 ,  H01L2224/27416 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48 ,  H01L2224/73104 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/81903 ,  H01L2224/83007 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Abstract translation: 一种包括半导体元件的半导体器件; 形成在半导体元件上的焊盘电极; 形成在半导体元件上的对准标记; 形成在焊盘电极上的连接电极; 以及形成为覆盖连接电极的底部填充树脂。 来自半导体元件的对准标记的高度大于连接电极的高度。

公开(公告)号：US07915743B2

公开(公告)日：2011-03-29

申请号：US12309324

申请日：2007-07-19

Applicant: Hideaki Ishizawa ,  Akinobu Hayakawa

Inventor： Hideaki Ishizawa ,  Akinobu Hayakawa

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00

CPC classification number: C09J11/04 ,  C08G59/42 ,  C08L63/00 ,  C09J11/08 ,  C09J163/00 ,  C09J2203/326 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/26135 ,  H01L2224/26165 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/83138 ,  H01L2224/83855 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01061 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2224/29099 ,  H01L2224/29199

Abstract: It is an object of the present invention to provide: an adhesive for electronic parts that makes it possible to accurately maintain a distance between electronic parts upon joining electronic parts such as two or more semiconductor chips and also to obtain reliable electronic parts such as a semiconductor device; a method for producing a semiconductor chip laminated body using the adhesive for electronic parts; and a semiconductor device using the adhesive for electronic parts.The present invention is an adhesive for electronic parts configured to join the electronic parts, which contains: an adhesive composition comprising a curing compound and a curing agent; and spacer particles having a CV value of 10% or less, a viscosity at 1 rpm being 200 Pa·s or less and a viscosity at 10 rpm being 100 Pa·s or less, upon being measured at 25° C. by using an E type viscometer, and a viscosity at 0.5 rpm being 1.4 to 3 times as large as the viscosity at 1 rpm, and the viscosity at 1 rpm being 2 to 5 times as large as the viscosity at 10 rpm.

Abstract translation: 本发明的目的是提供：一种用于电子部件的粘合剂，其可以在连接诸如两个或更多个半导体芯片的电子部件之后准确地保持电子部件之间的距离，并且还获得可靠的电子部件，例如半导体 设备; 一种使用电子部件用粘合剂制造半导体芯片层叠体的方法; 以及使用电子部件用粘合剂的半导体装置。 本发明是一种用于连接电子部件的电子部件的粘合剂，其包含：包含固化化合物和固化剂的粘合剂组合物; CV值为10％以下，1rpm时的粘度为200Pa·s以下，10rpm下的粘度为100Pa·s以下的间隔物颗粒，在25℃下使用 E型粘度计，0.5rpm时的粘度为1rpm时的粘度的1.4〜3倍，1rpm的粘度为10rpm时的粘度的2〜5倍。

公开(公告)号：US20160027760A1

公开(公告)日：2016-01-28

申请号：US14858065

申请日：2015-09-18

Applicant: Internatonal Business Machines Corporation

Inventor： Roy R. YU ,  Wilfried HAENSCH

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/18

CPC classification number: B32B37/02 ,  B32B37/12 ,  B32B38/1841 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/14 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/09 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/16147 ,  H01L2224/26135 ,  H01L2224/291 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/8314 ,  H01L2224/83141 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00

Abstract: A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory.

Abstract translation: 4D设备包括2D多核逻辑和通过存储器堆叠侧壁使用细间距T＆J连接连接的3D存储器堆栈。 堆叠中的3D存储器从原始晶片厚度减薄到不剩余的Si。 存储晶片顶部和底部表面上的舌形槽装置允许精确的堆叠对准。 存储器堆栈还在背面具有微通道以允许流体冷却。 存储器堆栈以固定的时钟周期距离进一步切割，并在其侧面翻转并且重新组装到模板上成为伪晶片格式。 组件的顶侧壁被抛光并用BEOL构建以扇出，并且使用T＆J细间距连接来连接到2D逻辑晶片。 存储器堆叠的另一面被抛光，扇形，并用C4焊料撞击。 本发明还包括一种制造该装置的方法。 另一方面，本发明包括一个4D处理和器件，每个芯片超过50×大于2D存储密度和超高密度存储器。

公开(公告)号：US20150364455A1

公开(公告)日：2015-12-17

申请号：US14723893

申请日：2015-05-28

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Malta) Ltd ,  STMicroelectronics S.r.l.

Inventor： Angelo Crobu ,  Kenneth Fonk ,  Romain Coffy

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/18 ,  G01L19/0084 ,  G01L19/147 ,  G01L19/148 ,  H01L23/24 ,  H01L23/3157 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1319 ,  H01L2224/16145 ,  H01L2224/26122 ,  H01L2224/26135 ,  H01L2224/29007 ,  H01L2224/29021 ,  H01L2224/29036 ,  H01L2224/32014 ,  H01L2224/32111 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/16151 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A stack of chips is formed by a first integrated-circuit chip and a second integrated-circuit chip. The chips have opposing faces which are separated from each other by an interposed spacer. The spacer is fastened by adhesion to only one of the opposing faces. The opposing faces are fastened to each other by a local adhesive which is separate from spacer.

Abstract translation: 一堆芯片由第一集成电路芯片和第二集成电路芯片形成。 芯片具有通过插入的间隔件彼此分离的相对面。 间隔件通过粘合固定到只有一个相对的面。 相对的面通过与间隔物分离的局部粘合剂彼此紧固。