公开(公告)号：US10528462B2

公开(公告)日：2020-01-07

申请号：US15276696

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam

IPC: G06F12/02 ,  G06F3/06

Abstract: A machine readable storage medium containing program code that when processed by a processor causes a method to be performed a method is described. The method includes executing a wear leveling routine by servicing cold data from a first queue in a non volatile storage device to write the cold data. The method also includes executing a garbage collection routing by servicing valid data from a second queue in the non volatile storage device to write the valid data. The method also includes servicing host write data from a third queue in the non volatile storage device to write the host write data wherein the first queue remains fixed and is serviced at a constant rate so that a runtime size of the third queue is not substantially affected by the wear leveling routine.

公开(公告)号：US10133668B2

公开(公告)日：2018-11-20

申请号：US15277377

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam

IPC: G06F11/00 ,  G06F12/0804 ,  G11C16/10 ,  G11C16/26 ,  G11C14/00 ,  G06F3/06 ,  G06F11/20

Abstract: Technologies for providing cross data storage device communication include a compute device to transmit, with a processor, a move request to a first data storage device. The first data storage device is to transmit, in response to the move request, a completion notification to the processor. Additionally, the compute device is to read, with the first data storage device, after transmitting the completion notification, a block of data from a first non-volatile memory of the first data storage device to a volatile memory of the compute device. The first data storage device is to transmit to the second data storage device a second move request to move the block of data. The second data storage device is to write the block of data from the volatile memory to a second non-volatile memory of the second data storage device.

公开(公告)号：US20180188978A1

公开(公告)日：2018-07-05

申请号：US15803107

申请日：2017-11-03

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam ,  Pranav Kalavade

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/7204 ,  G06F2212/7205

Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

公开(公告)号：US10008250B2

公开(公告)日：2018-06-26

申请号：US14671493

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam

IPC: G11C11/56 ,  G11C7/00 ,  G11C11/16 ,  G11C16/34 ,  G06F12/02 ,  G11C13/00 ,  G11C16/04

CPC classification number: G11C11/1675 ,  G06F12/0238 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/3495 ,  G11C2211/5641 ,  G11C2213/71

Abstract: Methods and apparatus related to cost optimized Single Level Cell (SLC) write buffering for Three Level Cell (TLC) Solid State Drives (SSDs) are described. In one embodiment, non-volatile memory includes a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell mode. A portion of the second region is moved from the multiple level cell mode to the SLC mode, without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory.

公开(公告)号：US09851905B1

公开(公告)日：2017-12-26

申请号：US15280898

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Anand S. Ramalingam ,  Pranav Kalavade ,  Aliasgar S. Madraswala

IPC: G11C7/00 ,  G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0611 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0802 ,  G06F13/16

Abstract: A non-volatile memory interface employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation. Memory control logic of the memory interface is configured to issue to the write operation suspend logic, a write operation resume command. The transaction control logic may be further configured to automatically suspend performing of a write operation in response to receipt of a read command. The transaction control logic may also be configured to automatically resume a previously suspended write operation in response to completion of a preemptive read operation by the memory.

公开(公告)号：US09811269B1

公开(公告)日：2017-11-07

申请号：US15395062

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam ,  Pranav Kalavade

IPC: G11C7/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/7204 ,  G06F2212/7205

Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

公开(公告)号：US09760281B2

公开(公告)日：2017-09-12

申请号：US14671968

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： Anand S. Ramalingam

IPC: G06F13/00 ,  G06F3/06 ,  G06F12/0895

CPC classification number: G06F3/0602 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F12/0895 ,  G06F13/16 ,  G06F2212/202 ,  G06F2212/60

Abstract: In one embodiment, sequential write stream management is employed to improve the sequential nature of write data placed in a storage such as a solid state drive, notwithstanding intermingling of write commands from various sequential and nonsequential streams from multiple processor nodes in a system. In one embodiment, write data from an identified sequential write stream is placed in a storage area assigned to that particular identified sequential write stream. In another aspect, detected sequential write streams are identified as a function of write velocity of the detected stream. Other aspects are described herein.