公开(公告)号：US20220130748A1

公开(公告)日：2022-04-28

申请号：US17567639

申请日：2022-01-03

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40 ,  H01L21/48

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

公开(公告)号：US11289263B2

公开(公告)日：2022-03-29

申请号：US15854460

申请日：2017-12-26

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Lauren A. Link ,  Andrew J. Brown

IPC: H01F27/28 ,  H01L23/522 ,  H01L49/02 ,  H01L23/538 ,  H01F17/00 ,  H01L21/768

Abstract: An electronic structure may be fabricated comprising an electronic substrate having at least one photo-imageable dielectric layer and an inductor embedded in the electronic substrate, wherein the inductor comprises a magnetic material layer disposed within a via formed in the at least one photo-imageable dielectric layer and an electrically conductive via extending through the magnetic material layer. The electronic structure may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

公开(公告)号：US10672859B2

公开(公告)日：2020-06-02

申请号：US16020590

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Sheng Li ,  Sai Vadlamani ,  Chong Zhang

IPC: H01L23/522 ,  H01L49/02 ,  H01F17/00 ,  H01L23/00

Abstract: An apparatus and method of forming a magnetic inductor circuit. A substrate is provided and a first magnetic layer is formed in contact with one layer of the substrate. A conductive trace is formed in contact with the first magnetic layer. A sacrificial cooper layer protects the magnetic material from wet chemistry process steps. A conductive connection is formed from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection formed by in-layer plating. A second magnetic layer is formed in contact with the conductive trace. Instead of a horizontal connection, a vertical conductive connection can be formed that is perpendicular to the magnetic layers, by drilling a first via in a second of the magnetic layers, forming a buildup layer, and drilling a second via through the buildup layer, where the buildup layer protects the magnetic layers from wet chemistry processes.

公开(公告)号：US20200075511A1

公开(公告)日：2020-03-05

申请号：US16119923

申请日：2018-08-31

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

公开(公告)号：US20190221345A1

公开(公告)日：2019-07-18

申请号：US15870302

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Rahul Jain ,  Kyu Oh Lee ,  Sheng C. Li ,  Andrew J. Brown ,  Lauren A. Link

IPC: H01F1/42 ,  H01L21/56 ,  H01F27/38 ,  B32B27/38 ,  C22C45/04 ,  H01F27/28

CPC classification number: H01F1/42 ,  B32B27/38 ,  C22C45/04 ,  H01F27/2804 ,  H01F27/38 ,  H01L21/56

Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

公开(公告)号：US11824013B2

公开(公告)日：2023-11-21

申请号：US16541734

申请日：2019-08-15

Applicant: INTEL CORPORATION

Inventor： Lauren A. Link ,  Andrew J. Brown ,  Sheng C. Li ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/351

Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

公开(公告)号：US11705389B2

公开(公告)日：2023-07-18

申请号：US16437420

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Luke Garner ,  Liwei Cheng ,  Lauren Link ,  Cheng Xu ,  Ying Wang ,  Bin Zou ,  Chong Zhang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49894

Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.

公开(公告)号：US11651902B2

公开(公告)日：2023-05-16

申请号：US16024715

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Andrew J. Brown ,  Prithwish Chatterjee ,  Sai Vadlamani ,  Lauren Link

IPC: H01L23/522 ,  H01G4/33 ,  H01L49/02

CPC classification number: H01G4/33 ,  H01L23/5222 ,  H01L28/40

Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.

公开(公告)号：US11552010B2

公开(公告)日：2023-01-10

申请号：US16603863

申请日：2017-05-12

Applicant: Intel Corporation

Inventor： Robert A. May ,  Andrew J. Brown ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta

IPC: H01L23/498 ,  C07D413/12 ,  C08G73/16 ,  C08K3/22 ,  C08K3/38 ,  C08K5/548 ,  C08K13/02 ,  H01L21/48

Abstract: The present disclosure is directed to systems and methods for providing a dielectric layer on a semiconductor substrate capable of supporting very high density interconnects (i.e., ≥100 IO/mm). The dielectric layer includes a maleimide polymer in which a thiol-terminated functional group crosslinks with an epoxy resin. The resultant dielectric material provides a dielectric constant of less than 3 and a dissipation factor of less than 0.001. Additionally, the thiol functional group forms coordination complexes with noble metals present in the conductive structures, thus by controlling the stoichiometry of epoxy to polyimide, the thiol-polyimide may beneficially provide an adhesion enhancer between the dielectric and noble metal conductive structures.

公开(公告)号：US11495552B2

公开(公告)日：2022-11-08

申请号：US16024702

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Thomas Sounart ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prithwish Chatterjee ,  Andrew J. Brown

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.