公开(公告)号：US11335395B2

公开(公告)日：2022-05-17

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  Christopher P. Mozak ,  James A. McCall ,  Akshith Vasanth ,  Bill Nale

IPC: G11C11/4072 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/406

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US11282561B2

公开(公告)日：2022-03-22

申请号：US17157826

申请日：2021-01-25

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US11093391B2

公开(公告)日：2021-08-17

申请号：US16557628

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Saher Abu Rahme ,  Christopher E. Cox ,  Joydeep Ray

IPC: G06F12/0804 ,  G06F12/0868 ,  G06F1/3225 ,  G06F3/06 ,  G06F12/0897

Abstract: A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

公开(公告)号：US11061590B2

公开(公告)日：2021-07-13

申请号：US16547197

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： Tonia G. Morris ,  Christopher P. Mozak ,  Christopher E. Cox

IPC: G06F3/06 ,  G11C11/4076 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02

Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

公开(公告)号：US11042315B2

公开(公告)日：2021-06-22

申请号：US15940499

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Christopher E. Cox ,  Navneet Dour ,  Asaf Rubinstein ,  Israel Diamand

IPC: G06F3/06 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/42

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

公开(公告)号：US10923859B2

公开(公告)日：2021-02-16

申请号：US16389781

申请日：2019-04-19

Applicant: Intel Corporation

Inventor： Jaejin Lee ,  Jun Liao ,  Xiang Li ,  George Vergis ,  Christopher E. Cox

IPC: H01R13/6471 ,  H05K5/00 ,  H05K5/02 ,  H01R12/73 ,  H05K1/18 ,  H01R12/70 ,  H01R12/72 ,  H01R13/6461 ,  H01R13/24

Abstract: Embodiments of the present disclosure relate to a connector to connect a printed circuit board (PCB) with a memory device, where the connector includes a housing couplable with the PCB; a first signal pin coupled with the housing, where the first signal pin includes a first portion that includes a first curve, and a second portion that extends from the first portion and includes a second curve; and a second signal pin coupled with the housing, where the second signal pin includes a third portion that includes a third curve, and a fourth portion that extends from the third portion and includes a fourth curve, where the first curve is curved in a first opposite direction relative to the third curve, and where the second curve is curved in a second opposite direction relative to the fourth curve.

公开(公告)号：US10541018B2

公开(公告)日：2020-01-21

申请号：US15716485

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： James A. McCall ,  Christopher P. Mozak ,  Christopher E. Cox ,  Yan Fu ,  Robert J. Friar ,  Hsien-Pao Yang

IPC: G11C11/40 ,  G11C11/4072 ,  G06F3/06

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

公开(公告)号：US10176138B2

公开(公告)日：2019-01-08

申请号：US15068128

申请日：2016-03-11

Applicant: INTEL CORPORATION

Inventor： Christopher E. Cox ,  Kuljit S. Bains

IPC: G06F3/00 ,  G06F13/12 ,  G06F13/40 ,  G06F13/38 ,  G06F11/30 ,  G06F11/22 ,  G06F11/34

Abstract: Techniques and mechanisms for configuring an integrated circuit to couple to, and exchange data with, a hardware interface. In an embodiment, the integrated circuit comprises a data channel including a plurality of bits, configuration logic, and a plurality of contacts including a first contact group and a second contact group. In response to a signal indicating connectivity of the integrated circuit to the interface, a mode of the configuration logic is selected to couple the plurality of bits to one of the first contact group and the second contact group.

公开(公告)号：US09948299B2

公开(公告)日：2018-04-17

申请号：US15462664

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Nadav Bonen ,  Christopher E. Cox ,  Alexey Kostinsky

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  G06F13/40 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

公开(公告)号：US11990172B2

公开(公告)日：2024-05-21

申请号：US18213231

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Bill Nale ,  Christopher E. Cox

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/4096

CPC classification number: G11C11/40611 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4096 ,  G11C11/40618

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.