公开(公告)号：US11737208B2

公开(公告)日：2023-08-22

申请号：US16268813

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/498

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

公开(公告)号：US11574874B2

公开(公告)日：2023-02-07

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Srinivas V. Pietambaram ,  Frank Truong ,  Praneeth Akkinepally ,  Andrew J. Brown ,  Lauren A. Link ,  Prithwish Chatterjee

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US11276634B2

公开(公告)日：2022-03-15

申请号：US16607601

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  David Unruh ,  Frank Truong ,  Kyu Oh Lee ,  Junnan Zhao ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

公开(公告)号：US20220005638A1

公开(公告)日：2022-01-06

申请号：US17482861

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Frank Truong ,  Shivasubramanian Balasubramanian

IPC: H01F1/20 ,  H01F27/28 ,  H01L23/00 ,  H01L23/64 ,  H01L23/498 ,  H01F17/00

Abstract: A magnetic material may be fabricated with a plurality of magnetic filler particles dispersed within a carrier material, wherein at last one of the magnetic filler particles may comprise a ferromagnetic core coated with an inert material to form a shell surrounding the ferromagnetic core. Such a coating may allow for the use of ferromagnetic materials for forming embedded inductors in package substrates without the risk of being incompatible with fabrication processes used to form these package substrates.

公开(公告)号：US20200075473A1

公开(公告)日：2020-03-05

申请号：US16607601

申请日：2017-05-23

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  David Unruh ,  Frank Truong ,  Kyu Oh Lee ,  Junnan Zhao ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

公开(公告)号：US20190287841A1

公开(公告)日：2019-09-19

申请号：US15922749

申请日：2018-03-15

Applicant: Intel Corporation

Inventor： Frank Truong ,  Praneeth Akkinepally ,  Chelsea M. Groves ,  Whitney M. Bryks ,  Jason M. Gamba ,  Brandon C. Marin

IPC: H01L21/683 ,  H01L21/687 ,  C09J5/06

Abstract: A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.