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    HYBRID PITCH THROUGH HOLE CONNECTOR
    21.
    发明申请
    HYBRID PITCH THROUGH HOLE CONNECTOR 有权

    公开(公告)号：US20210153351A1

    公开(公告)日：2021-05-20

    申请号：US17127829

    申请日：2020-12-18

    Applicant: Intel Corporation

    Inventor： Xiang LI ,  George VERGIS ,  Jeffrey KRIEGER

    IPC: H05K1/11 ,  H01R12/52 ,  H05K5/02 ,  H05K1/18 ,  G11C5/06

    Abstract: Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.

    CONNECTOR PINS FOR REDUCING CROSSTALK
    24.
    发明公开
    CONNECTOR PINS FOR REDUCING CROSSTALK 审中-公开

    公开(公告)号：US20240145996A1

    公开(公告)日：2024-05-02

    申请号：US18395069

    申请日：2023-12-22

    Applicant: Intel Corporation

    Inventor： Xiang LI ,  George VERGIS ,  James A. McCALL

    IPC: H01R13/6471 ,  H01R12/73

    CPC classification number: H01R13/6471 ,  H01R12/737

    Abstract: A new connector implemented with connector pins to reduce crosstalk significantly improves memory channel electrical performance for next generation DDR (double data rate) technology. To reduce crosstalk the connector pins include pins with three different pin shapes, including two differently shaped signal pins and a ground pin that combines the shapes of the signal pins. The shaped pins enables them to be positioned in a connector so that each signal pin can have its own independent and separate signal return path on a single ground pin. In this manner, crosstalk can be significantly reduced.

    AUTONOMOUS BACKSIDE DATA BUFFER TO MEMORY CHIP WRITE TRAINING CONTROL
    25.
    发明申请
    AUTONOMOUS BACKSIDE DATA BUFFER TO MEMORY CHIP WRITE TRAINING CONTROL 有权

    公开(公告)号：US20230136268A1

    公开(公告)日：2023-05-04

    申请号：US18086634

    申请日：2022-12-21

    Applicant: Intel Corporation

    Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  John V. LOVELACE ,  George VERGIS

    IPC: G06F3/06

    Abstract: An apparatus is described. The apparatus includes data buffer to memory chip write training circuitry. The data buffer to memory chip write training circuitry to send MDQ/MDQS phase relationship programming information, write commands and read commands to the data buffer chips for multiple write training iterations without a host memory controller having provided the MDQ/MDQS phase relationship programming information, the write commands and the read commands to the data buffer to memory chip write training circuitry.

    MULTIPLEXED RANKS (MR) WITH PSEUDO BURST LENGTH 32 (BL32)
    26.
    发明申请
    MULTIPLEXED RANKS (MR) WITH PSEUDO BURST LENGTH 32 (BL32) 有权

    公开(公告)号：US20230071117A1

    公开(公告)日：2023-03-09

    申请号：US17987687

    申请日：2022-11-15

    Applicant: Intel Corporation

    Inventor： Hussein ALAMEER ,  Bill NALE ,  George VERGIS ,  Rajat AGARWAL

    IPC: G06F3/06

    Abstract: A memory module has a registering clock driver (RCD) that issues two column address strobe (CAS) commands with a single memory access command to exchange a double amount of data per dynamic random access memory (DRAM) device per memory access command. With double the amount of data per DRAM device, the memory module can provide double the pseudo channels as compared to a memory module where a single CAS command is issued per access command. The RCD can time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the command/address (CA) bus.

    MODULAR MEZZANINE POWER VOLTAGE REGULATOR MODULE FOR MEMORY MODULES
    27.
    发明申请
    MODULAR MEZZANINE POWER VOLTAGE REGULATOR MODULE FOR MEMORY MODULES 有权

    公开(公告)号：US20220391007A1

    公开(公告)日：2022-12-08

    申请号：US17886366

    申请日：2022-08-11

    Applicant: Intel Corporation

    Inventor： Min Suet LIM ,  George VERGIS ,  Stephen P. CHRISTIANSON ,  Ankita TIWARI ,  Virendra Vikramsinh ADSURE

    IPC: G06F1/3234 ,  H01L23/14

    Abstract: Apparatus, assemblies, and platforms employing modular power voltage regulator (VR) modules to provide power to memory modules. A power VR module includes VR circuitry integrated on or coupled to a substrate with wiring coupling the VR circuitry to connector elements in first and second connector means. An assembly further includes a pair of memory modules (e.g., DDR) that are coupled to a power VR module via mating connector means. The connector means may be coupled using a Compression Mount Technology (CMT) connector disposed between arrays of CMT contact pads on the power VR module and the memory modules, or may comprise BGAs, PGAs, and LGAs. The power VR module receives one or more input voltages via one or both memory module and provide various output voltages to each of the memory modules to power memory devices and other circuitry on those modules.

    MEMORY MODULE BASED DATA BUFFER COMMUNICATION BUS TRAINING
    28.
    发明申请
    MEMORY MODULE BASED DATA BUFFER COMMUNICATION BUS TRAINING 有权

    公开(公告)号：US20220301608A1

    公开(公告)日：2022-09-22

    申请号：US17830118

    申请日：2022-06-01

    Applicant: Intel Corporation

    Inventor： Saravanan SETHURAMAN ,  Tonia M. ROSE ,  George VERGIS ,  John V. LOVELACE

    IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

    Abstract: An apparatus is described. The apparatus includes a register clock redriver (RCD) chip comprising a buffer communication (BCOM) interface, a BCOM training control circuit and BCOM training control register space, the BCOM training control circuit is to: transmit a series of symbol transmissions over the BCOM interface to a data buffer with different respective clock phase delays to sweep the symbol transmissions within an eye window; collect resultants of the symbol transmissions from the data buffer; and, perform an analysis on the resultants to determine an appropriate clock phase within the eye window.

    APPARATUS AND METHOD FOR PER MEMORY CHIP ADDRESSING
    29.
    发明申请
    APPARATUS AND METHOD FOR PER MEMORY CHIP ADDRESSING 有权

    公开(公告)号：US20220276958A1

    公开(公告)日：2022-09-01

    申请号：US17747950

    申请日：2022-05-18

    Applicant: Intel Corporation

    Inventor： Saravanan SETHURAMAN ,  George VERGIS ,  Tonia M. ROSE ,  John R. GOLES ,  John V. LOVELACE

    IPC: G06F12/06

    Abstract: A memory chip is described. The memory chip includes self identification circuitry to self identify the memory chip. The self identification circuitry is to determine a resistance of a resistor and correlate the memory chip's identity to the resistance. A registering clock driver (RCD) chip is described. The RCD chip includes a controller. The controller is to receive provisional IDs (PIDs) from memory chips on a same memory module as the RCD chip. The controller is to program the memory chips with respective logical IDs (LIDs) based on a correlation of the PIDs and the LIDs.

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