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公开(公告)号：US12243611B2
公开(公告)日：2025-03-04
申请号：US17856897
申请日：2022-07-01
Applicant: Intel Corporation
Inventor： Minki Cho , Daniel Nemiroff , Carlos Tokunaga , James W. Tschanz , Kah Meng Yeem , Yaxin Shui
IPC: G11C5/00
Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.
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公开(公告)号：US11921529B2
公开(公告)日：2024-03-05
申请号：US16914174
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Yi-Chun Shih , Kaushik Mazumdar , Stephen T. Kim , Rinkle Jain , James W. Tschanz , Muhammad M. Khellah
Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
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公开(公告)号：US09762241B1
公开(公告)日：2017-09-12
申请号：US15198124
申请日：2016-06-30
Applicant: Intel Corporation
Inventor： Charles Augustine , Suriya Ashok Kumar , Carlos Tokunaga , James W. Tschanz
IPC: H04L9/08 , H03K19/003 , H03K19/177 , H04L9/32
CPC classification number: H03K19/00315 , H03K3/0315 , H03K3/84 , H03K19/1776 , H04L9/3278
Abstract: Some embodiments include apparatus and methods using a first ring oscillator, a second ring oscillator, and circuit coupled to the first and second ring oscillators. The first ring oscillator includes a first memory cell and a first plurality of stages coupled to the first memory cell. The second ring oscillator includes a second memory cell and a second plurality of stages coupled to the second memory cell. The circuit includes a first input node coupled to an output node of the first ring oscillator and a second input node coupled to an output node of the second ring oscillator. In one of such embodiments, the circuit can operate to generate identification information to authenticate the apparatus.
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公开(公告)号：US09680472B2
公开(公告)日：2017-06-13
申请号：US15182486
申请日：2016-06-14
Applicant: INTEL CORPORATION
Inventor： Amit R. Trivedi , Jaydeep P. Kulkarni , Carlos Tokunaga , Muhammad M. Khellah , James W. Tschanz
IPC: H03K19/0175 , H03K19/0185
CPC classification number: H03K19/018521 , H03K3/356113
Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.
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公开(公告)号：US09666257B2
公开(公告)日：2017-05-30
申请号：US14696050
申请日：2015-04-24
Applicant: INTEL CORPORATION
Inventor： Charles Augustine , Shigeki Tomishima , James W. Tschanz , Shih-Lien L. Lu
CPC classification number: G11C11/1659 , G11C11/1657 , G11C11/1673 , G11C11/1675 , G11C11/1693
Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.
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Patent Agency Ranking
公开(公告)号：US09621163B2
公开(公告)日：2017-04-11
申请号：US14569569
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Amit R. Trivedi , Jaydeep P. Kulkarni , Dinesh Somasekhar , Muhammad M. Khellah , Carlos Tokunaga , James W. Tschanz
IPC: H03L5/00 , H03K19/0175
CPC classification number: H03K19/017509
Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.
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公开(公告)号：US09594625B2
公开(公告)日：2017-03-14
申请号：US14878985
申请日：2015-10-08
Applicant: INTEL CORPORATION
Inventor： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC: G06F11/07 , G06F1/10 , H03K3/037 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G06F1/10 , G06F11/0706 , G06F11/0757 , G06F11/0793 , H03K3/0375
Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
Abstract translation: 提供了具有错误检测的顺序电路。 例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。 在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。
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28.发明申请公开(公告)号：US20160314838A1
公开(公告)日：2016-10-27
申请号：US15187646
申请日：2016-06-20
Applicant: Intel Corporation
Inventor： Charles Augustine , Wei Wu , Shigeki Tomishima , Shih-Lien L. Lu , James W. Tschanz
CPC classification number: G11C13/0069 , G11C7/1006 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0021 , G11C13/0033 , G11C13/004 , G11C2013/0042 , G11C2213/79 , G11C2213/82
Abstract: Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.
Abstract translation: 描述了一种装置，其包括：互补电阻存储器位单元; 以及耦合到所述互补电阻存储器位单元的读出放大器，其中所述读出放大器包括：第一输出节点; 以及第一晶体管，其可操作以在所述第一输出节点上产生确定性输出。
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公开(公告)号：US09406313B2
公开(公告)日：2016-08-02
申请号：US14222284
申请日：2014-03-21
Applicant: Intel Corporation
Inventor： Joseph F. Ryan , James W. Tschanz , Willem M. Beltman
CPC classification number: G10L25/78 , G10L15/28 , G10L25/24 , G10L25/48 , H04R3/00 , H04R29/004 , H04R2499/11
Abstract: An apparatus for adjusting a microphone sampling rate, the apparatus including an input to receive an audio signal from a microphone and a front-end processing module. The front-end processing module is to generate a plurality of frames from the audio signal received by the microphone, determine a noise profile using the plurality of frames, and adjust a sampling rate of the microphone based on the determined noise profile.
Abstract translation: 一种用于调节麦克风采样率的装置，该装置包括用于从麦克风接收音频信号的输入端和前端处理模块。 前端处理模块是根据由麦克风接收的音频信号产生多个帧，使用多个帧确定噪声分布，并且基于确定的噪声分布来调整麦克风的采样率。
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公开(公告)号：US09385722B2
公开(公告)日：2016-07-05
申请号：US14553934
申请日：2014-11-25
Applicant: Intel Corporation
Inventor： Amit R. Trivedi , Jaydeep P. Kulkarni , Carlos Tokunaga , Muhammad M. Khellah , James W. Tschanz
IPC: H03K19/0175 , H03K19/0185
CPC classification number: H03K19/018521 , H03K3/356113
Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.
Abstract translation: 实施例包括用于在低电压域和高电压域之间电压移位数据信号的装置，方法和系统。 在实施例中，电压电平移位器电路可以包括自适应保持器电路，增强的可中断电源电路和/或电容升压电路，以减小由电压电平移位器电路支持的低电压域的最小电压。 可以描述和要求保护其他实施例。
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