公开(公告)号：US20210011853A1

公开(公告)日：2021-01-14

申请号：US16939158

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Cristiano J. Ferreira ,  Bo Qiu ,  Ajit Krisshna Nandyal Lakshman ,  Nikhil Talpallikar ,  Deepak Gandiga Shivakumar ,  Brandt M. Guttridge ,  Kim Pallister ,  Frank J. Soqui ,  Anand Srivatsa ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jonathan Kennedy

IPC: G06F12/10 ,  G06F12/0875 ,  G06F12/0811 ,  G06T1/60

Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.

公开(公告)号：USD772186S1

公开(公告)日：2016-11-22

申请号：US29528773

申请日：2015-06-01

Applicant: Intel Corporation

Designer： Peter Wyatt ,  Sayan Lahiri ,  Christine Kim ,  Aleksander Magi ,  Jianfang Zhu ,  Misha Singh ,  Kerry Lee Forell

公开(公告)号：US20240045490A1

公开(公告)日：2024-02-08

申请号：US18449890

申请日：2023-08-15

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US11422616B2

公开(公告)日：2022-08-23

申请号：US16830485

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US20220186716A1

公开(公告)日：2022-06-16

申请号：US17561605

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Mark J. Gallina ,  Min Suet Lim ,  Jianfang Zhu

IPC: F03G7/06 ,  H02N10/00

Abstract: Particular embodiments described herein provide for a flexible vapor chamber with shape memory material for an electronic device. In an example, the electronic device can include a flexible vapor chamber and shape memory material coupled to the shape memory material. When the shape memory material is activated, the shape memory material moves a portion of the flexible vapor chamber to a position that helps with heat dissipation of heat collected by the flexible vapor chamber.

公开(公告)号：US20220113781A1

公开(公告)日：2022-04-14

申请号：US17557034

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  Jianfang Zhu ,  Ivan Chen ,  Deepak Samuel Kirubakaran ,  Rajshree Chabukswar ,  Richard Winterton ,  Houfei Chen

IPC: G06F1/324

Abstract: Methods and apparatus for bi-directional control of computing unit frequency are disclosed. An example apparatus to control a frequency of a computing unit includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to determine a performance hint from a first register, the performance hint corresponding to a requested performance of the computing unit for executing a thread associated with software, determine power and performance (PnP) statistics pertaining to the thread from a second register, control the frequency of the computing unit based on the performance hint and the PnP statistics, and provide a pressure of the computing unit to the software.

公开(公告)号：US20220113757A1

公开(公告)日：2022-04-14

申请号：US17558118

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jin Yan ,  Hui Xiong ,  Jianfang Zhu ,  Felipe Gonzalez ,  Mark MacDonald ,  Daniel Ragland ,  Rodny Rodriguez ,  Matthew Fife ,  Yifan Li ,  Kristoffer Fleming

IPC: G06F1/08 ,  G06F1/20

Abstract: Apparatus, systems, and methods for intelligent tuning of overclocking frequency are disclosed. An example apparatus includes trial control circuitry to execute an optimization model to select first values for overclocking parameters of a processor, the first values associated with a first trial, and perform benchmark testing of the processor when the processor is operating based on the first values; trial evaluation circuitry to calculate a first score for the first trial based on the benchmark testing; and model updating circuitry to perform a comparison of the first score to a second score, the second score associated with a second trial for second values for the overclocking parameters, the second values different than the first values; and select one of the first values or the second values to overclock the processor based on the comparison.

公开(公告)号：US20200264698A1

公开(公告)日：2020-08-20

申请号：US16793539

申请日：2020-02-18

Applicant: Intel Corporation

Inventor： Karthik Veeramani ,  Jianfang Zhu ,  Sayan Lahiri ,  Bo Qiu ,  Bradley A. Jackson ,  Paul S. Diefenbaugh ,  Kim Pallister

IPC: G06F3/01 ,  G06F3/03 ,  G06F1/16 ,  G06F3/042 ,  G02B27/01

Abstract: An embodiment of a graphics apparatus may include an image generator, and a gesture tracker communicatively coupled to the image generator. The image generator may be configured to generate an image of a virtual input device, the gesture tracker may be configured to determine a position of a user's finger relative to the virtual input device, and the image generator may be further configured to generate an image of a virtual finger based on the determined position of the user's finger relative to the virtual input device. Other embodiments are disclosed and claimed.

公开(公告)号：US20180293173A1

公开(公告)日：2018-10-11

申请号：US15483741

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Cristiano J. Ferreira ,  Bo Qiu ,  Ajit Krisshna Nandyal Lakshman ,  Nikhil Talpallikar ,  Deepak Gandiga Shivakumar ,  Brandt M. Guttridge ,  Kim Pallister ,  Frank J. Soqui ,  Anand Srivatsa ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jonathan Kennedy

IPC: G06F12/10

Abstract: An embodiment of an electronic processing system may include an application processor, system memory communicatively coupled to the application processor, a graphics processor communicatively coupled to the application processor, graphics memory communicatively coupled to the graphics processor, and persistent storage media communicatively coupled to the application processor and the graphics processor to store one or more graphics assets, wherein the graphics processor is to access the one or more graphics asset mapped from the persistent storage media. The persistent storage media may include a low latency, high capacity, and byte-addressable nonvolatile memory. The one or more graphics assets may include one or more of a mega-texture and terrain data. Other embodiments are disclosed and claimed.

公开(公告)号：US20180006485A1

公开(公告)日：2018-01-04

申请号：US15201418

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Bo Qiu ,  Bradley A. Jackson ,  Sayan Lahiri ,  James B. Kirkland, JR. ,  Ahmed Omer

IPC: H02J7/02 ,  H02J50/40 ,  H02J50/10

CPC classification number: H02J7/025 ,  H02J7/0042 ,  H02J7/0044 ,  H02J50/10 ,  H02J50/40

Abstract: In one example a docking mat for an electronic device comprises a substrate defining a first major surface on which the electronic device may be positioned, a power source coupling, a plurality of power grids embedded in the first major surface and electrically coupled to the power source coupling, wherein a portion of the power grids extend above the first major surface. Other examples may be described.