公开(公告)号：US10453535B2

公开(公告)日：2019-10-22

申请号：US14922611

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Akira Goda ,  Pranav Kalavade ,  Krishna K. Parat ,  Hiroyuki Sanda

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C16/34

Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.

公开(公告)号：US09792997B2

公开(公告)日：2017-10-17

申请号：US15183582

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US09245645B2

公开(公告)日：2016-01-26

申请号：US13963629

申请日：2013-08-09

Applicant: INTEL CORPORATION

Inventor： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

Abstract: Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例包括用于存储器件的多脉冲编程的技术和配置。 在一个实施例中，一种方法包括应用多个脉冲来对存储器件的一个或多个多电平单元（MLC）进行编程，其中多个脉冲的各个脉冲与一个或多个MLC的各个级别对应，并且在施加多个 脉冲，验证一个或多个MLC的各个级别的编程。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150311087A1

公开(公告)日：2015-10-29

申请号：US14635482

申请日：2015-03-02

Applicant: INTEL CORPORATION

Inventor： Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L21/308 ,  H01L29/49 ,  H01L27/115

CPC classification number: H01L21/3088 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/32134 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4933 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.

Abstract translation: 公开了一种用于形成非易失性存储器件的非易失性存储器件和方法。 在制造存储器件期间，使用钨硅化物作为蚀刻停止层代替常规使用的氧化铝以形成具有高纵横比的通道柱。 使用钨硅化物可用于消除不期望的蚀刻停止凹部和当通常使用Al氧化物蚀刻停止层时形成的不需要的浮动栅极。