公开(公告)号：US20210090990A1

公开(公告)日：2021-03-25

申请号：US16579077

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Florian GSTREIN ,  Leonard P. GULER ,  Charles H. WALLACE ,  Paul A. NYHUS ,  Curtis WARD ,  Mohit K. HARAN ,  Reken PATEL

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/66

Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

公开(公告)号：US20240113019A1

公开(公告)日：2024-04-04

申请号：US17956775

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohit K. HARAN ,  Nikhil MEHTA ,  Charles H. WALLACE ,  Tahir GHANI ,  Sukru YEMENICIOGLU

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76877 ,  H01L23/5226

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge. A second conductive via is in a second opening in the second ILD layer, the second conductive via in contact with a second one of the plurality of conductive lines, the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines, and the second conductive via having a straight edge, the straight edge of the second conductive via facing the straight edge of the first conductive via.

公开(公告)号：US20230326794A1

公开(公告)日：2023-10-12

申请号：US18207047

申请日：2023-06-07

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael HARPER ,  Suzanne S. RICH ,  Charles H. WALLACE ,  Curtis WARD ,  Richard E. SCHENKER ,  Paul NYHUS ,  Mohit K. HARAN ,  Reken PATEL ,  Swaminathan SIVAKUMAR

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/823412 ,  H01L21/823475

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.

公开(公告)号：US20230317731A1

公开(公告)日：2023-10-05

申请号：US17709378

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mauro J. KOBRINSKY ,  Mohit K. HARAN ,  Marni NABORS ,  Tahir GHANI ,  Charles H. WALLACE ,  Allen B. GARDINER ,  Sukru YEMENICIOGLU

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L21/76283

Abstract: Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.

公开(公告)号：US20230197854A1

公开(公告)日：2023-06-22

申请号：US17553161

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Mohammad HASAN ,  Aryan NAVABI-SHIRAZI ,  Allen B. GARDINER

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/42392

Abstract: Integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, and methods of fabricating integrated circuit structures having a dielectric anchor and confined epitaxial source or drain structure, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A confined epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A dielectric anchor is laterally spaced apart from the plurality of horizontally stacked nanowires and recessed into a first portion of the STI structure, the dielectric anchor having an uppermost surface below an uppermost surface of the confined epitaxial source or drain structure.

公开(公告)号：US20230187441A1

公开(公告)日：2023-06-15

申请号：US17548027

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Sukru YEMENICIOGLU ,  Chanaka D. MUNASINGHE

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0669 ,  H01L29/785

Abstract: Integrated circuit structures having trench contact flyover structures, and methods of fabricating integrated circuit structures having trench contact flyover structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate dielectric material layer is surrounding the plurality of horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure, the conductive trench contact structure electrically isolated from the epitaxial source or drain structure.

公开(公告)号：US20220393007A1

公开(公告)日：2022-12-08

申请号：US17340747

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohit K. HARAN ,  Tahir GHANI ,  Charles H. WALLACE

IPC: H01L29/417 ,  H01L27/088

Abstract: Narrow conductive via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. A dielectric liner is along the plurality of dielectric spacers over the plurality of gate structures. A plurality of conductive pin structures is between the dielectric liner, individual ones of the plurality of conductive pin structures on corresponding ones of the plurality of gate structures.

公开(公告)号：US20220310516A1

公开(公告)日：2022-09-29

申请号：US17841479

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Atul MADHAVAN ,  Nicholas J. KYBERT ,  Mohit K. HARAN ,  Hiten KOTHARI

IPC: H01L23/535 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51

Abstract: Contact over active gate (COAG) structures with etch stop layers, and methods of fabricating contact over active gate (COAG) structures using etch stop layers, are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. A second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. An interlayer dielectric material is on the second dielectric etch stop layer.

公开(公告)号：US20200185271A1

公开(公告)日：2020-06-11

申请号：US16637930

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Reken PATEL ,  Hyunsoo PARK ,  Mohit K. HARAN ,  Debashish BASU ,  Curtis W. WARD ,  Ruth A. Brain

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.

公开(公告)号：US20190206728A1

公开(公告)日：2019-07-04

申请号：US16329172

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Marvin Y. PAIK ,  Hyunsoo PARK ,  Mohit K. HARAN ,  Alexander F. KAPLAN ,  Ruth A. BRAIN

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528

Abstract: Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.