公开(公告)号：US20220366630A1

公开(公告)日：2022-11-17

申请号：US17876358

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20220182592A1

公开(公告)日：2022-06-09

申请号：US17526633

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20220066931A1

公开(公告)日：2022-03-03

申请号：US17310540

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： JOYDEEP RAY ,  NIRANJAN COORAY ,  SUBRAMANIAM MAIYURAN ,  ALTUG KOKER ,  PRASOONKUMAR SURTI ,  VARGHESE GEORGE ,  VALENTIN ANDREI ,  ABHISHEK APPU ,  GUADALUPE GARCIA ,  PATTABHIRAMAN K ,  SUNGYE KIM ,  SANJAY KUMAR ,  PRATIK MAROLIA ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VASANTH RANGANATHAN ,  WILLIAM SADLER ,  LAKSHMINARAYANAN STRIRAMASSARMA

IPC: G06F12/0802

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20210149811A1

公开(公告)日：2021-05-20

申请号：US16685224

申请日：2019-11-15

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  KARTHIK VAIDYANATHAN ,  KAROL SZERSZEN

IPC: G06F12/0884 ,  G06F12/0837 ,  H03M7/30 ,  G06F9/30

Abstract: An apparatus to facilitate packing compressed data is disclosed. The apparatus includes compression hardware to compress memory data into a plurality of compressed data components and packing hardware to receive the plurality of compressed data components and pack a first of the plurality of compressed data components beginning at a least significant bit (LSB) location of a compressed bit stream and pack a second of the plurality of compressed data components beginning at a most significant bit (MSB) of the compressed bit stream.

公开(公告)号：US20200310973A1

公开(公告)日：2020-10-01

申请号：US16366266

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ALTUG KOKER ,  VIDHYA KRISHNAN ,  RONALD W. SILVAS ,  JOHN H. FEIT ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY ,  ABHISHEK R. APPU

IPC: G06F12/0837 ,  G06F9/38 ,  H04L9/06 ,  G06F16/907

Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

公开(公告)号：US20200211263A1

公开(公告)日：2020-07-02

申请号：US16235906

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： SCOTT JANUS ,  PRASOONKUMAR SURTI ,  KARTHIK VAIDYANATHAN ,  ALEXEY SUPIKOV ,  GABOR LIKTOR ,  CARSTEN BENTHIN ,  PHILIP LAWS ,  MICHAEL DOYLE

IPC: G06T15/06 ,  G06T17/00 ,  G06T15/00 ,  G06T1/60

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20200043218A1

公开(公告)日：2020-02-06

申请号：US16056222

申请日：2018-08-06

Applicant: Intel Corporation

Inventor： KARTHIK VAIDYANATHAN ,  WON-JONG LEE ,  GABOR LIKTOR ,  JOHN G. GIERACH ,  PAWEL MAJEWSKI ,  PRASOONKUMAR SURTI ,  CARSTEN BENTHIN ,  Sven WOOP ,  THOMAS RAOUX

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/80

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US20180308211A1

公开(公告)日：2018-10-25

申请号：US15493261

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： PRASOONKUMAR SURTI ,  ABHISHEK R. APPU

IPC: G06T1/60 ,  G06T1/20 ,  G06T5/00 ,  G06T11/40 ,  G06T11/00 ,  G06T9/00

CPC classification number: G06T9/00 ,  G06T1/20 ,  G06T5/002 ,  G06T11/001 ,  G06T11/40 ,  G06T2210/52

Abstract: One embodiment provides for a general-purpose graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine color data for multiple sample locations of each pixel in a set of pixels and to contiguously pack the color data for the multiple sample locations of each pixel for storage to a multisample render target.

公开(公告)号：US20160163094A1

公开(公告)日：2016-06-09

申请号：US14561711

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： PRASOONKUMAR SURTI ,  LARRY SEILER ,  ADAM Z. LEIBEL

IPC: G06T15/80 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: Systems and methods may provide for receiving a pixel shader and sending the pixel shader to shader bypass hardware if the pixel shader and a render target associated with the pixel shader satisfy a simplicity condition. In one example, the shader bypass hardware is dedicated to pixel shaders and associated render targets that satisfy the simplicity condition.

Abstract translation: 如果像素着色器和与像素着色器相关联的渲染目标满足简单条件，系统和方法可以提供接收像素着色器并将像素着色器发送到着色器旁路硬件。 在一个示例中，着色器旁路硬件专用于满足简单条件的像素着色器和相关联的渲染目标。