公开(公告)号：US20240112730A1

公开(公告)日：2024-04-04

申请号：US17957945

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Nazila Haratipour ,  Saima Siddiqui ,  Uygar Avci ,  Chia-Ching Lin

IPC: G11C13/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C13/0026 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0069 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  G11C2213/79

Abstract: Techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (FE) resistive junction. In an embodiment, a memory cell comprises a transistor and a FE resistive junction structure which is coupled to the transistor. The FE resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a FE oxide or a FE semiconductor. The FE resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. A current flow through the FE resistive junction structure is characterized by thermionic emission through a Schottky barrier at an interface with one of the electrode structures. In another embodiment, the FE resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.

公开(公告)号：US20230200079A1

公开(公告)日：2023-06-22

申请号：US17555207

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Tanay A. Gosavi ,  Uygar E. Avci ,  Sou-Chi Chang ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  Ashish Verma Penumatcha ,  John J. Plombon ,  Ian Alexander Young

IPC: H01L27/11514 ,  H01L49/02 ,  H01L29/51

CPC classification number: H01L27/11514 ,  H01L28/65 ,  H01L29/516

Abstract: A first type of ferroelectric capacitor comprises electrodes and an insulating layer comprising ferroelectric oxides. In some embodiments, the electrodes and the insulating layer comprise perovskite ferroelectric oxides. A second type of ferroelectric capacitor comprises a ferroelectric insulating layer comprising certain monochalcogenides. Both types of ferroelectric capacitors can have a coercive voltage that is less than one volt. Such capacitors are attractive for use in low-voltage non-volatile embedded memories for next-generation semiconductor manufacturing technologies.

公开(公告)号：US20230197643A1

公开(公告)日：2023-06-22

申请号：US17560062

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  Sou-Chi Chang ,  Scott Clendenning ,  Matthew Metz

IPC: H01L23/64 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L23/642 ,  H01L21/0228 ,  H01L23/5286

Abstract: IC die and/or IC die packages including capacitors with a pyrochlore-based insulator material. The pyrochlore-based insulator material comprises a compound of a species A and a species B, each comprising one or more rare earths or metals. In the pyrochlore-based insulator material, oxygen content is advantageously more than three times and less than four times the amount of either of species A or B with crystalline pyrochlore phases having the composition A2B2O7. Within a capacitor, the pyrochlore-based insulator may be amorphous and/or may have one or more crystalline phases. The pyrochlore-based insulator has an exceedingly high relative permittivity of 50-100, or more. The pyrochlore-based insulator material may be deposited at low temperatures compatible with interconnect metallization processes practiced in IC die manufacture as well as IC die packaging.

公开(公告)号：US20220199833A1

公开(公告)日：2022-06-23

申请号：US17133197

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Uygar Avci ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Sou-Chi Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1159 ,  H01L29/51

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

公开(公告)号：US11316027B2

公开(公告)日：2022-04-26

申请号：US16833375

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Nazila Haratipour ,  Tanay Gosavi ,  I-Cheng Tung ,  Seung Hoon Sung ,  Ian Young ,  Jack Kavalieros ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/24 ,  H01L29/92

Abstract: A capacitor device includes a first electrode having a first metal alloy or a metal oxide, a relaxor ferroelectric layer adjacent to the first electrode, where the ferroelectric layer includes oxygen and two or more of lead, barium, manganese, zirconium, titanium, iron, bismuth, strontium, neodymium, potassium, or niobium and a second electrode coupled with the relaxor ferroelectric layer, where the second electrode includes a second metal alloy or a second metal oxide.

公开(公告)号：US20200286687A1

公开(公告)日：2020-09-10

申请号：US16296085

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Nazila Haratipour ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H01L27/108 ,  H01L49/02 ,  G11C11/22

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

公开(公告)号：US20250105136A1

公开(公告)日：2025-03-27

申请号：US18473887

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel A. Elsherbini ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Thomas Lee Sounart ,  Tushar Kanti Talukdar ,  Johanna Marie Swan ,  Uygar Avci

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: Capacitors for use with integrated circuit packages are disclosed. An example apparatus includes a semiconductor substrate, a metal layer coupled to the semiconductor substrate, a dielectric layer coupled to the metal layer, the dielectric layer including a capacitor disposed therein, and an interface layer positioned between the metal layer and the dielectric layer, the interface layer in contact with the dielectric layer and in contact with the metal layer.

公开(公告)号：US12166122B2

公开(公告)日：2024-12-10

申请号：US17133197

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Uygar Avci ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Sou-Chi Chang

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.

公开(公告)号：US11532439B2

公开(公告)日：2022-12-20

申请号：US16296085

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Nazila Haratipour ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: G11C16/10 ,  H01G7/06 ,  G11C11/22 ,  H01L27/108 ,  H01L49/02

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

公开(公告)号：US20220352358A1

公开(公告)日：2022-11-03

申请号：US17833662

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Sou-Chi Chang ,  Dmitri Nikonov ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/82 ,  G11C11/16 ,  H01F10/32

Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as, EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.