公开(公告)号：US20200273952A1

公开(公告)日：2020-08-27

申请号：US15930627

申请日：2020-05-13

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  BENJAMIN CHU-KUNG ,  SEUNG HOON SUNG ,  JACK T. KAVALIEROS ,  TAHIR GHANI ,  HAROLD W. KENNEL

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

公开(公告)号：US20190214479A1

公开(公告)日：2019-07-11

申请号：US16326844

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  SEUNG HOON SUNG ,  BENJAMIN CHU-KUNG ,  TAHIR GHANI

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/417 ,  H01L29/785

Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.

公开(公告)号：US20190115466A1

公开(公告)日：2019-04-18

申请号：US16214946

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/04 ,  H01L29/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：US20180337235A1

公开(公告)日：2018-11-22

申请号：US15776996

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： WILLY RACHMADY ,  MATTHEW V. METZ ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  NADIA M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The subfin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20180323310A1

公开(公告)日：2018-11-08

申请号：US15529432

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L29/778 ,  H01L27/06

CPC classification number: H01L29/78681 ,  H01L27/0605 ,  H01L29/1054 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170358645A1

公开(公告)日：2017-12-14

申请号：US15525269

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  GLENN A. GLASS

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/775 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

公开(公告)号：US20170345900A1

公开(公告)日：2017-11-30

申请号：US15527221

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/205 ,  H01L21/02 ,  H01L21/18

CPC classification number: H01L29/205 ,  H01L21/02455 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/182 ,  H01L21/185

Abstract: Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170323962A1

公开(公告)日：2017-11-09

申请号：US15525164

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  HAROLD W. KENNEL ,  GLENN A. GLASS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7781

Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

公开(公告)号：US20170221724A1

公开(公告)日：2017-08-03

申请号：US15489569

申请日：2017-04-17

Applicant: INTEL CORPORATION

Inventor： ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  RAVI PILLARISETTY ,  NILOY MUKHERJEE ,  JACK T. KAVALIEROS ,  ROZA KOTLYAR ,  WILLY RACHMADY ,  MARK Y. LIU

IPC: H01L21/3215 ,  H01L29/06 ,  H01L29/778 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

CPC classification number: H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

公开(公告)号：US20170162661A1

公开(公告)日：2017-06-08

申请号：US15436336

申请日：2017-02-17

Applicant: INTEL CORPORATION

Inventor： MICHAEL G. HAVERTY ,  SADASIVAN SHANKAR ,  TAHIR GHANI ,  SEONGJUN PARK

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/283 ,  H01L21/3205 ,  H01L23/482 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.