公开(公告)号：US20220392808A1

公开(公告)日：2022-12-08

申请号：US17339160

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Mohammad HASAN ,  William HSU ,  Biswajeet GUHA ,  Charles H. WALLACE ,  Tahir GHANI ,  Sean PURSEL ,  Tsuan-Chung CHANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.

公开(公告)号：US20220093592A1

公开(公告)日：2022-03-24

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael K. HARPER ,  William HSU ,  Biswajeet GUHA ,  Tahir GHANI ,  Niels ZUSSSBLATT ,  Jeffrey Miles TAN ,  Benjamin KRIEGEL ,  Mohit K. HARAN ,  Reken PATEL ,  Oleg GOLONZKA ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  G11C5/06

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

公开(公告)号：US20210202534A1

公开(公告)日：2021-07-01

申请号：US16727370

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Chung-Hsun LIN ,  Biswajeet GUHA ,  William HSU ,  Stephen CEA ,  Tahir GHANI

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/84 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.

公开(公告)号：US20240363628A1

公开(公告)日：2024-10-31

申请号：US18767458

申请日：2024-07-09

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20240120335A1

公开(公告)日：2024-04-11

申请号：US18390952

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Biswajeet GUHA ,  William HSU ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

公开(公告)号：US20240030348A1

公开(公告)日：2024-01-25

申请号：US18374959

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/02603 ,  H01L21/823481 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/42392 ,  H01L2029/7858

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US20220416042A1

公开(公告)日：2022-12-29

申请号：US17358478

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： William HSU ,  Leonard P. GULER ,  Vivek THIRTHA ,  Nitesh KUMAR ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having reduced gate height structures and subfins, and method of fabricating gate-all-around integrated circuit structures having reduced gate height structures, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a subfin, and an isolation structure on either side of the subfin. A gate stack is over the plurality of nanowires, around individual nanowires, and over the subfin. Gate spacers are on either side of the gate stack, and a dielectric capping material is inside the gate spacers with shoulder portions inside the gate stack.

公开(公告)号：US20220416041A1

公开(公告)日：2022-12-29

申请号：US17357895

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Mohammad HASAN ,  William HSU ,  Biswajeet GUHA ,  Oleg GOLONZKA ,  Tahir GHANI ,  Vivek THIRTHA ,  Nitesh KUMAR

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making semiconductor devices. In an embodiment, a semiconductor device comprises a substrate, where the substrate is a dielectric material, and a vertical stack of semiconductor channels over the substrate. In an embodiment, the semiconductor device further comprises a source at a first end of the semiconductor channels, a drain at a second end of the semiconductor channels, and a barrier between a bottom surface of the source and the substrate.

公开(公告)号：US20220336668A1

公开(公告)日：2022-10-20

申请号：US17850799

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Bruce E. BEATTIE ,  Leonard GULER ,  Biswajeet GUHA ,  Jun Sung KANG ,  William HSU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

公开(公告)号：US20220246721A1

公开(公告)日：2022-08-04

申请号：US17725471

申请日：2022-04-20

Applicant: INTEL CORPORATION

Inventor： William HSU ,  Biswajeet GUHA ,  Leonard GULER ,  Souvik CHAKRABARTY ,  Jun Sung KANG ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.