公开(公告)号：US09411683B2

公开(公告)日：2016-08-09

申请号：US14141215

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Zion S. Kwok ,  Andre Lei ,  Scott Nelson

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  G06F11/08

CPC classification number: G06F11/1076 ,  G06F11/08 ,  G06F11/1012 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3715

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to load an error correction codeword retrieved from a memory and apply a first error correction decoder to decode the error correction codeword, wherein the first error correction decoder implements a bit-flipping error correction algorithm which utilizes a variable bit-flipping threshold to determine whether to flip a bit in an error correction codeword. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了存储器中用于纠错的装置，系统和方法。 在一个实施例中，存储器控制器包括用于加载从存储器检索的纠错码字的逻辑，并且应用第一纠错解码器来解码纠错码字，其中第一纠错解码器实现位移翻转纠错算法，其使用 可变位跳转阈值，以确定是否在纠错码字中翻转位。 还公开并要求保护其他实施例。

公开(公告)号：US09246516B2

公开(公告)日：2016-01-26

申请号：US13723062

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Zion S. Kwok

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/37

CPC classification number: H03M13/1515 ,  H03M13/152 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/1575 ,  H03M13/3715 ,  H03M13/6502

Abstract: Techniques for error correction of encoded data are described. In some examples, error correction code (ECC) information for the ECC encoded data is received that indicates the ECC encoded data includes one or more errors. A determination is then made as to whether the ECC encoded data includes a single error, two errors or more than two errors. If the ECC encoded data includes a single error, an error location of the error is identified. If the ECC encoded data includes two errors, first and second error locations are identified. If the ECC encoded data includes more than two errors, separate error locations are identified for the more than two errors. The single error, the two errors or the more than two errors is/are corrected and the ECC encoded data is then be decoded.

Abstract translation: 描述编码数据的纠错技术。 在一些示例中，接收用于ECC编码数据的纠错码（ECC）信息，其指示ECC编码数据包括一个或多个错误。 然后确定ECC编码数据是否包括单个错误，两个错误或多于两个错误。 如果ECC编码数据包含单个错误，则识别错误的错误位置。 如果ECC编码数据包括两个错误，则识别出第一和第二错误位置。 如果ECC编码数据包含两个以上的错误，则会识别出两个以上错误的单独错误位置。 对单个错误，两个错误或两个以上错误进行校正，然后对ECC编码数据进行解码。

公开(公告)号：US20140181615A1

公开(公告)日：2014-06-26

申请号：US13725809

申请日：2012-12-21

Applicant: INTEL CORPORATION

Inventor： Zion S. Kwok

IPC: H03M13/29

CPC classification number: H03M13/2906 ,  G06F11/00 ,  G06F11/1012 ,  H03M13/095 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

Abstract: Techniques and mechanisms to facilitate data error detection by a memory controller. In an embodiment, the memory controller calculates, for each of a plurality of data blocks, a respective result based on a first metadata value and data of that data block, where the first metadata value describes a characteristic which is common to each of the plurality of data blocks. With each such calculated result, the memory controller further performs a respective error detection analysis, wherein such analysis is based on a retrieved error correction code for a corresponding one of the plurality of data blocks. In another embodiment, a single version of the metadata value is stored by the memory controller, where the single version of the metadata value is made available to facilitate error detection for any of the plurality of data blocks.

Abstract translation: 用于促进存储器控制器进行数据错误检测的技术和机制。 在一个实施例中，存储器控制器针对多个数据块中的每一个计算基于第一元数据值和该数据块的数据的相应结果，其中第一元数据值描述了多个数据块中的每一个共同的特性 的数据块。 利用每个这样的计算结果，存储器控制器还执行相应的错误检测分析，其中这种分析基于用于多个数据块中的对应一个的检索到的纠错码。 在另一个实施例中，元数据值的单一版本由存储器控制器存储，其中元数据值的单一版本可用于促进多个数据块中的任一个的错误检测。

公开(公告)号：US12169435B2

公开(公告)日：2024-12-17

申请号：US17171430

申请日：2021-02-09

Applicant: Intel Corporation

Inventor： Debarnab Mitra ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: G06F11/10 ,  H03M13/11

Abstract: An embodiment of an electronic apparatus comprises one or more substrates, and logic coupled to the one or more substrates, the logic to detect unreliable messages between check nodes and variable nodes in association with an error correction operation, determine respective degrees of unreliability for the unreliable messages, and reduce an influence of the unreliable messages on the error correction operation, as compared to an influence of reliable messages between the check nodes and the variables nodes, based on the determined respective degrees of unreliability. Other embodiments are disclosed and claimed.

公开(公告)号：US11204718B2

公开(公告)日：2021-12-21

申请号：US16586428

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Zion S. Kwok ,  Muthukumar Swaminathan

IPC: G06F3/06

Abstract: Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.

公开(公告)号：US11182240B2

公开(公告)日：2021-11-23

申请号：US17032567

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: G06F11/10 ,  H03M13/21 ,  H03M13/29 ,  H03M13/00 ,  H03M13/11 ,  H03M13/39

Abstract: Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.

公开(公告)号：US11086714B2

公开(公告)日：2021-08-10

申请号：US16578039

申请日：2019-09-20

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Zion S. Kwok

IPC: G06F11/00 ,  G06F11/10 ,  G06F7/58 ,  G06F7/76 ,  H03M13/11

Abstract: Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device.

公开(公告)号：US20190102248A1

公开(公告)日：2019-04-04

申请号：US15721291

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani ,  Zion S. Kwok

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/37

Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

公开(公告)号：US20190044541A1

公开(公告)日：2019-02-07

申请号：US15860513

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Zion S. Kwok

IPC: H03M13/15 ,  H03M13/00

Abstract: Devices, systems, and methods that reduce the latency of detecting that a codeword is uncorrectable are disclosed and described. Such devices, systems, and methods allow the determination that a codeword is uncorrectable prior to determining error locations in the codeword, thus eliminating the need for such an error location search.

公开(公告)号：US09934859B1

公开(公告)日：2018-04-03

申请号：US15391763

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Prashant S. Damle ,  Kunal A. Khochare ,  Philip Hillier ,  Jeffrey W. Ryden ,  Richard P. Mangold

IPC: G11C16/10 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028

Abstract: In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.