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    Zinc stannate ohmic contacts for p-type gallium nitride
    22.
    发明授权
    Zinc stannate ohmic contacts for p-type gallium nitride 有权
    用于p型氮化镓的锡酸锡欧姆接触

    公开(公告)号：US09246062B2

    公开(公告)日：2016-01-26

    申请号：US14259387

    申请日：2014-04-23

    Applicant: Intermolecular, Inc.

    Inventor： Jianhua Hu ,  Heng Kai Hsu ,  Tong Ju ,  Minh Huu Le ,  Sandeep Nijhawan ,  Teresa B. Sapirman

    IPC: H01L21/00 ,  H01L33/42 ,  H01L33/32

    CPC classification number: H01L33/42 ,  H01L33/32 ,  H01L33/40 ,  H01L33/483 ,  H01L2933/0016

    Abstract: Transparent ohmic contacts to p-GaN and other high-work-function (≧4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.

    Abstract translation: 由锡酸锡（例如ZnSnO 3）制造对p-GaN和其它高功函数（≥4.2eV）的半导体的透明欧姆接触。 ZnO和SnO2可以从单独的靶溅射并退火以形成锡酸锌。 可以在1:2和2:1之间的范围内调整Zn：Sn比，以优化特定半导体和感兴趣的波长的带隙，功函数，电导率和透明度。 可以通过使锡酸锌结晶，通过掺入高达5重量％的Al或In或两者来改善电导率。

    Novel Method to Grow In-Situ Crystalline IGZO
    24.
    发明申请
    Novel Method to Grow In-Situ Crystalline IGZO 有权
    增加原位结晶IGZO的新方法

    公开(公告)号：US20150279670A1

    公开(公告)日：2015-10-01

    申请号：US14549158

    申请日：2014-11-20

    Applicant: Intermolecular Inc.

    Inventor： Seon-Mee Cho ,  Stuart Brinkley ,  Anh Duong ,  Majid Gharghi ,  Sang Lee ,  Minh Huu Le ,  Karl Littau ,  Jingang Su

    IPC: H01L21/02 ,  H01L29/786

    CPC classification number: H01L21/02565 ,  H01L21/02554 ,  H01L21/02631 ,  H01L29/7869

    Abstract: A co-sputter technique is used to deposit In—Ga—Zn—O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300 C results in a substrate temperature of about 165 C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, without the need of a subsequent anneal treatment.

    Abstract translation: 使用共溅射技术使用PVD沉积In-Ga-Zn-O膜。 膜在包括氧和氩的气氛中沉积。 约300℃的加热器设定值导致衬底温度为约165℃。一个靶包括In，Ga，Zn和O的合金，原子比为In：Ga：Zn为约1:1:1的原子比。 第二靶标包括氧化锌的化合物。 膜以沉积状态呈现c轴对准的结晶（CAAC）相，而不需要随后的退火处理。

    IGZO with Intra-Layer Variations and Methods for Forming the Same
    26.
    发明申请
    IGZO with Intra-Layer Variations and Methods for Forming the Same 审中-公开
    具有层间变化的IGZO及其形成方法

    公开(公告)号：US20150187574A1

    公开(公告)日：2015-07-02

    申请号：US14140797

    申请日：2013-12-26

    Applicant: LG Display Co. Ltd. ,  Intermolecular Inc.

    Inventor： Minh Huu Le ,  Yoon-Kyung Chang ,  Seon-Mee Cho ,  Min-Cheol Kim ,  Sang Lee ,  Kwon-Sik Park ,  Woosup Shin

    IPC: H01L21/02 ,  H01L29/66

    CPC classification number: H01L21/02631 ,  H01L21/02422 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

    Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO) with intra-layer variations and methods for forming such IGZO. At least a portion of a substrate is positioned in a processing chamber. A first sub-layer of an IGZO layer is formed above the at least a portion of the substrate while the at least a portion of the substrate is in the processing chamber. The first sub-layer of the IGZO layer is formed using a first set of processing conditions. A second sub-layer of the IGZO layer is formed above the first sub-layer of the IGZO layer while the at least a portion of the substrate is in the processing chamber. The second sub-layer of the IGZO layer is formed using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.

    Abstract translation: 本文所述的实施方案提供了具有层内变化的晶体铟镓锌氧化物（IGZO）的方法和用于形成这种IGZO的方法。 衬底的至少一部分位于处理室中。 在基板的至少一部分上方形成IGZO层的第一子层，同时基板的至少一部分位于处理室中。 使用第一组处理条件形成IGZO层的第一子层。 IGZO层的第二子层形成在IGZO层的第一子层的上方，而基板的至少一部分在处理室内。 IGZO层的第二子层使用第二组处理条件形成。 第二组处理条件与第一组处理条件不同。

    Low-emissivity panels including magnetic layers
    28.
    发明授权
    Low-emissivity panels including magnetic layers 有权
    低辐射面板包括磁性层

    公开(公告)号：US09013782B2

    公开(公告)日：2015-04-21

    申请号：US14144319

    申请日：2013-12-30

    Applicant: Intermolecular Inc.

    Inventor： Guowen Ding ,  Minh Huu Le

    IPC: G02B26/00 ,  C23C14/08 ,  G02F1/09 ,  B29D11/00 ,  G02B5/26 ,  C03C17/36 ,  C23C14/14

    CPC classification number: G02B5/208 ,  B29D11/00865 ,  C03C17/36 ,  C03C17/3626 ,  C03C17/3639 ,  C03C17/3644 ,  C03C17/366 ,  C03C17/3681 ,  C03C23/007 ,  C03C2217/43 ,  C03C2217/48 ,  C03C2218/154 ,  C23C14/083 ,  C23C14/085 ,  C23C14/14 ,  C23C14/22 ,  E06B9/24 ,  E06B2009/2417 ,  E06B2009/2464 ,  G02B5/26 ,  G02F1/091 ,  G02F2001/094 ,  Y10T428/24975 ,  Y10T428/265

    Abstract: Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a first substrate. The first substrate may have a first side and a second side. The low emissivity panels may also include a magnetic fluid layer deposited over the first side of the first substrate and a reflective layer deposited over the second side of the first substrate. The magnetic fluid layer may include magnetic particles. The reflective layer may include a conductive material configured to conduct an electrical current and generate a magnetic field. The magnetic field may be configured to change an orientation of the magnetic particles in the magnetic fluid layer and a transmissivity of the magnetic fluid layer within a visible spectrum. The low emissivity panels may also include a first bus and a second bus deposited along opposite edges of the reflective layer and electrically connected to the reflective layer.

    Abstract translation: 本文公开了用于形成可包括第一基板的低辐射面板的系统，方法和装置。 第一基板可以具有第一侧和第二侧。 低辐射面板还可以包括沉积在第一衬底的第一侧上的磁性流体层和沉积在第一衬底的第二侧上的反射层。 磁性流体层可以包括磁性颗粒。 反射层可以包括被配置为传导电流并产生磁场的导电材料。 磁场可以被配置为改变磁性流体层中的磁性颗粒的取向和磁性流体层在可见光谱内的透射率。 低辐射面板还可以包括沿着反射层的相对边缘沉积并电连接到反射层的第一总线和第二总线。

    Barrier Layers for Silver Reflective Coatings and HPC Workflows for Rapid Screening of Materials for Such Barrier Layers
    29.
    发明申请
    Barrier Layers for Silver Reflective Coatings and HPC Workflows for Rapid Screening of Materials for Such Barrier Layers 有权
    银色反射涂层屏障层和HPC工作流程，用于快速筛选这种阻挡层的材料

    公开(公告)号：US20150104569A1

    公开(公告)日：2015-04-16

    申请号：US14574755

    申请日：2014-12-18

    Applicant: Intermolecular Inc.

    Inventor： Guizhen Zhang ,  Jeremy Cheng ,  Guowen Ding ,  Minh Huu Le ,  Daniel Schweigert ,  Yu Wang

    IPC: C23C14/22 ,  C23C14/34 ,  C23C14/14

    CPC classification number: C23C14/22 ,  C03C17/36 ,  C03C17/3605 ,  C03C17/3618 ,  C03C17/3644 ,  C03C17/3652 ,  C03C17/366 ,  C03C17/3681 ,  C23C14/0036 ,  C23C14/042 ,  C23C14/14 ,  C23C14/34 ,  G02B1/12 ,  G02B1/14 ,  Y10T428/12542 ,  Y10T428/12549 ,  Y10T428/12611 ,  Y10T428/12778 ,  Y10T428/31678

    Abstract: Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium—25-30%, titanium and aluminum—30%-35% each. The barrier layer may be co-sputtered in a reactive or inert-environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer.

    Abstract translation: 提供了半导体衬底的高生产率组合（HPC）测试方法，每个包括多个现场隔离区域。 位置隔离区域用于测试布置在银反射器上的阻挡层的不同组成和/或结构。 经测试的阻挡层可以包括镍，铬，钛和铝中的全部或至少两种。 在一些实施例中，阻挡层包括氧。 该组合允许使用具有高透明度的相对薄的阻挡层（例如5-30埃厚），同时为银反射器提供足够的保护。 阻挡层中的镍的量可以是5-10重量％，铬25-30％，钛和铝30％-35％。 阻挡层可以在反应性或惰性环境中使用包括所有四种金属的一种或多种目标共溅射。 物品可以包括多个银反射器，每个具有其自己的阻挡层。

    Resistive random access memory cells having doped current limiting layers
    30.
    发明授权
    Resistive random access memory cells having doped current limiting layers 有权
    具有掺杂限流层的电阻随机存取存储单元

    公开(公告)号：US08912518B2

    公开(公告)日：2014-12-16

    申请号：US13671824

    申请日：2012-11-08

    Applicant: Intermolecular, Inc.

    Inventor： David Chi ,  Vidyut Gopal ,  Minh Huu Le ,  Minh Anh Nguyen ,  Dipankar Pramanik ,  Milind Weling

    IPC: H01L29/02 ,  H01L47/00 ,  G11C11/00 ,  H01L45/00 ,  G11C13/00

    CPC classification number: H01L45/145 ,  G11C13/0007 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/146 ,  H01L45/1616

    Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.

    Abstract translation: 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由掺杂的金属氧化物和/或氮化物形成的限流层。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温退火时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压可以为至少约8V。 这种电流限制层的一些实例包括掺杂有铌的氧化钛，掺杂有锑的氧化锡和掺杂有铝的氧化锌。 掺杂剂和基材可以作为单独的子层沉积，然后通过退火重新分布，或者可以使用反应溅射或共溅射共沉积。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

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