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    Confined defect profiling within resistive random memory access cells
    22.
    发明授权
    Confined defect profiling within resistive random memory access cells 有权
    电阻式随机存储器存取单元中的限制缺陷分析

    公开(公告)号：US09269896B2

    公开(公告)日：2016-02-23

    申请号：US14519376

    申请日：2014-10-21

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Vidyut Gopal ,  Chien-Lan Hsueh

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L45/10 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

    Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.

    Abstract translation: 提供了电阻随机存取存储器（ReRAM）单元及其制造方法。 可以对包括缺陷源层，缺陷阻挡层和设置在缺陷源层和缺陷阻挡层之间的缺陷受主层的堆叠进行退火。 在退火过程中，缺陷以可控方式从缺陷源层转移到缺陷受体层。 同时，缺陷不会转移到缺陷阻挡层中，从而在缺陷受体层内形成最低浓度区。 该区域负责电阻交换。 精确控制区域的尺寸和区域内的缺陷浓度允许ReRAM单元的电阻开关特性得到显着改善。 在一些实施例中，缺陷源层包括氮氧化铝，缺陷阻挡层包括氮化钛，缺陷受主层包括氧化铝。

    Embedded Nonvolatile Memory Elements Having Resistive Switching Characteristics
    23.
    发明申请
    Embedded Nonvolatile Memory Elements Having Resistive Switching Characteristics 审中-公开
    具有电阻开关特性的嵌入式非易失性存储器元件

    公开(公告)号：US20150325788A1

    公开(公告)日：2015-11-12

    申请号：US14806263

    申请日：2015-07-22

    Applicant: Intermolecular Inc.

    Inventor： Imran Hashim ,  Tony P. Chiang ,  Vidyut Gopal ,  Yun Wang

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1608 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

    Abstract translation: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件（例如逻辑和数字信号处理组件）的集成电路芯片中。 在一些实施例中，所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极，而另一个电极连接到信号线。

    Atomic layer deposition of metal oxide materials for memory applications
    24.
    发明授权
    Atomic layer deposition of metal oxide materials for memory applications 有权
    用于记忆应用的金属氧化物材料的原子层沉积

    公开(公告)号：US08883655B2

    公开(公告)日：2014-11-11

    申请号：US13897050

    申请日：2013-05-17

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

    IPC: H01L21/31 ,  H01L21/469 ,  H01L45/00 ,  H01L21/02 ,  C23C16/455 ,  C23C16/40 ,  H01L27/24

    CPC classification number: H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

    Abstract translation: 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

    Bilayered Oxide Structures for ReRAM Cells
    26.
    发明申请
    Bilayered Oxide Structures for ReRAM Cells 审中-公开
    用于ReRAM电池的双层氧化物结构

    公开(公告)号：US20140175360A1

    公开(公告)日：2014-06-26

    申请号：US13721358

    申请日：2012-12-20

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Mihir Tendulkar ,  Vidyut Gopal ,  Imran Hashim ,  Randall J. Higuchi ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1625

    Abstract: Provided are resistive random access memory (ReRAM) cells having bi-layered metal oxide structures. The layers of a bi-layered structure may have different compositions and thicknesses. Specifically, one layer may be thinner than the other layer, sometimes as much as 5 to 20 times thinner. The thinner layer may be less than 30 Angstroms thick or even less than 10 Angstroms thick. The thinner layer is generally more oxygen rich than the thicker layer. Oxygen deficiency of the thinner layer may be less than 5 atomic percent or even less than 2 atomic percent. In some embodiments, a highest oxidation state metal oxide may be used to form a thinner layer. The thinner layer typically directly interfaces with one of the electrodes, such as an electrode made from doped polysilicon. Combining these specifically configured layers into the bi-layered structure allows improving forming and operating characteristics of ReRAM cells.

    Abstract translation: 提供了具有双层金属氧化物结构的电阻随机存取存储器（ReRAM）单元。 双层结构的层可以具有不同的组成和厚度。 具体地说，一层可以比另一层薄一些，有时可以减薄5至20倍。 较薄的层可以小于30埃厚或甚至小于10埃厚。 较薄的层通常比较厚的层富氧。 较薄层的缺氧可能小于5原子％或甚至小于2原子％。 在一些实施方案中，可以使用最高氧化态金属氧化物来形成较薄的层。 较薄的层通常直接与一个电极（例如由掺杂多晶硅制成的电极）接合。 将这些特定配置的层组合成双层结构允许改善ReRAM单元的成形和操作特性。

    Methods and Vehicles for High Productivity Combinatorial Testing of Materials for Resistive Random Access Memory Cells
    27.
    发明申请
    Methods and Vehicles for High Productivity Combinatorial Testing of Materials for Resistive Random Access Memory Cells 审中-公开
    用于电阻式随机存取存储器单元的材料的高生产率组合测试的方法和车辆

    公开(公告)号：US20140154859A1

    公开(公告)日：2014-06-05

    申请号：US13705516

    申请日：2012-12-05

    Applicant: INTERMOLECULAR INC.

    Inventor： Vidyut Gopal ,  Tony P. Chiang ,  Imran Hashim ,  Randall J. Higuchi ,  Robert A. Huertas ,  Hieu Pham ,  Yun Wang

    IPC: H01L49/02

    CPC classification number: H01L22/34 ,  H01L45/08 ,  H01L45/145

    Abstract: Provided are methods for processing different materials on the same substrate for high throughput screening of multiple ReRAM materials. A substrate may be divided into multiple site isolated regions, each region including one or more base structures operable as bottom electrodes of ReRAM cells. Different test samples may be formed over these base structures in a combinatorial manner. Specifically, each site isolated region may receive a test sample that has a different characteristic than at least one other sample provided in another region. The test samples may have different compositions and/or thicknesses or be deposited using different techniques. These different samples are then etched in the same operation to form portions of the samples. Each portion is substantially larger than the corresponding base structure and fully covers this base structure to protect the interface between the base structure and the portion during etching.

    Abstract translation: 提供了在同一基板上处理不同材料的方法，用于多个ReRAM材料的高通量筛选。 衬底可以被分成多个位置隔离区域，每个区域包括可操作为ReRAM单元的底部电极的一个或多个基底结构。 可以以组合的方式在这些基础结构上形成不同的测试样品。 具体地说，每个位置隔离区域可以接收具有与另一区域中提供的至少一个其他样品不同的特性的测试样品。 测试样品可以具有不同的组成和/或厚度或使用不同的技术沉积。 然后在相同的操作中蚀刻这些不同的样品以形成样品的一部分。 每个部分基本上大于对应的基部结构，并且完全覆盖该基部结构以在蚀刻期间保护基部结构和该部分之间的界面。

    Resistive Random Access Memory Cells Having Doped Current Limiting layers
    28.
    发明申请
    Resistive Random Access Memory Cells Having Doped Current Limiting layers 有权
    具有掺杂电流限制层的电阻随机存取存储器单元

    公开(公告)号：US20140124725A1

    公开(公告)日：2014-05-08

    申请号：US13671824

    申请日：2012-11-08

    Applicant: INTERMOLECULAR, INC.

    Inventor： David Chi ,  Vidyut Gopal ,  Minh Huu Le ,  Minh Anh Nguyen ,  Dipankar Pramanik ,  Milind Weling

    IPC: H01L45/00

    CPC classification number: H01L45/145 ,  G11C13/0007 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/146 ,  H01L45/1616

    Abstract: Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.

    Abstract translation: 提供了诸如电阻随机存取存储器（ReRAM）单元的半导体器件，其包括由掺杂的金属氧化物和/或氮化物形成的限流层。 这些限流层可具有至少约1欧姆 - 厘米的电阻率。 即使当这些层受到强电场和/或高温退火时，也保持该电阻率水平。 在一些实施例中，限流层的击穿电压可以为至少约8V。 这种电流限制层的一些实例包括掺杂有铌的氧化钛，掺杂有锑的氧化锡和掺杂有铝的氧化锌。 掺杂剂和基材可以作为单独的子层沉积，然后通过退火重新分布，或者可以使用反应溅射或共溅射共沉积。 层的高电阻率允许在保持其性能的同时缩小包括这些层的半导体器件的尺寸。

    Transition metal oxide bilayers
    29.
    发明授权
    Transition metal oxide bilayers 有权
    过渡金属氧化物双层

    公开(公告)号：US08704203B2

    公开(公告)日：2014-04-22

    申请号：US13971467

    申请日：2013-08-20

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Hieu Pham ,  Vidyut Gopal ,  Imran Hashim ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi ,  Hong Sheng Yang

    IPC: H01L29/02

    CPC classification number: H01L45/08 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

    Abstract: Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.

    Abstract translation: 本发明的实施例包括非易失性存储器元件和包括非易失性存储元件的存储器件。 还公开了形成非易失性存储元件的方法。 非易失性存储元件包括第一电极层，第二电极层和设置在第一和第二电极层之间的多个氧化物层。 氧化物层中的一个具有线性电阻和亚化学计量组成，另一个氧化物层具有双稳态电阻和近化学计量组成。 优选地，两个氧化物层厚度的总和在约和之间，并且具有双稳态电阻的氧化物层具有在总厚度的约25％至约75％之间的厚度。 在一个实施例中，氧化物层在具有受控的氩气和氧气的气氛中使用反应溅射形成。

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