公开(公告)号：US20140084420A1

公开(公告)日：2014-03-27

申请号：US13627179

申请日：2012-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Kevin K. Chan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L21/331 ,  H01L29/732

CPC classification number: H01L29/7371 ,  H01L21/82285 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7378

Abstract: A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening.

Abstract translation: 一种形成异质结双极晶体管的方法。 该方法包括提供包括至少本征基极区域和发射极基座区域的结构。 在本征基区上形成堆叠。 堆叠包括多晶硅层和顶部牺牲氧化物层。 在结构中形成沟槽。 沟槽围绕内在的基极区域和叠层。 在堆叠周围的两个区域形成一个非本征基。 外部基极通过选择性外延生长工艺形成，以在沟槽上形成桥。 桥梁连接两个地区。 在堆栈中提供一个开口。 开口暴露了内在基础区域的一部分。 在开口中形成发射体。

公开(公告)号：US10164597B2

公开(公告)日：2018-12-25

申请号：US15691272

申请日：2017-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H03H7/00 ,  H03H9/00 ,  H03H3/007 ,  H03H9/56 ,  H03H9/10 ,  H03H9/24 ,  G06F17/50 ,  H03H3/08 ,  H03H9/02 ,  H03H9/54 ,  H03H9/64 ,  H03H9/15 ,  H03H3/02

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.

公开(公告)号：US09607929B2

公开(公告)日：2017-03-28

申请号：US14825778

申请日：2015-08-13

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  Yoba Amoah ,  Jeffrey P. Gambino ,  Christine A. Leggett ,  Max L. Lifson ,  Charles F. Musante ,  Sruthi Samala ,  David C. Thomas

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate.

公开(公告)号：US20150255404A1

公开(公告)日：2015-09-10

申请号：US14195940

申请日：2014-03-04

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  Yoba Amoah ,  Jeffrey P. Gambino ,  Christine A. Leggett ,  Max L. Lifson ,  Charles F. Musante ,  Sruthi Samala ,  David C. Thomas

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate.

Abstract translation: 一种包括通过基板的厚度形成贯通基板的方法，从基板的前侧到基板的背面测量基板的厚度，去除基板的第一部分以形成开口 衬底的背面，使得衬底的第二部分保持与贯穿衬底通孔的垂直侧壁直接接触，并用与衬底相比具有较低弹性模量的替代材料填充该开口。

公开(公告)号：US09106854B2

公开(公告)日：2015-08-11

申请号：US14449557

申请日：2014-08-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  Richard J. Rassel

IPC: H04N5/359 ,  H01L27/146 ,  H04N5/3745 ,  H04N5/353 ,  H04N5/378

CPC classification number: H04N5/3595 ,  H01L27/14603 ,  H01L27/14609 ,  H04N5/3532 ,  H04N5/359 ,  H04N5/3745 ,  H04N5/378

Abstract: A reference pixel sensor cell (e.g., global shutter) with hold node for leakage cancellation, methods of manufacture and design structure is provided. A pixel array includes one or more reference pixel sensor cells dispersed locally throughout active light sensing regions. The one or more reference pixel sensor cells provides a reference signal used to correct for photon generated leakage signals which vary by locality within the active light sensing regions.

Abstract translation: 提供了具有用于泄漏消除的保持节点的参考像素传感器单元（例如，全局快门），制造方法和设计结构。 像素阵列包括在有源光感测区域局部分散的一个或多个参考像素传感器单元。 一个或多个参考像素传感器单元提供用于校正由于有源光感测区域内的局部性而变化的光子产生的泄漏信号的参考信号。

公开(公告)号：US20150206961A1

公开(公告)日：2015-07-23

申请号：US14160630

申请日：2014-01-22

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  James S. Dunn ,  Blaine J. Gross ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L21/28 ,  H01L29/165 ,  H01L29/15 ,  H01L29/06 ,  H01L21/02 ,  G06F17/50 ,  H01L29/161

CPC classification number: H01L29/808 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  H01L21/28026 ,  H01L21/306 ,  H01L21/8232 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66901 ,  H01L29/66924 ,  H01L29/7782 ,  H01L29/8124

Abstract: At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

Abstract translation: 在包括衬底，沟道和上栅极层的层堆叠中形成的至少一个隔离沟槽限定沟道层中的沟道。 来自隔离沟槽的横向蚀刻可以在衬底和上部栅极层中形成侧向空腔，以基本上同时形成自对准的下部栅极和上部栅极。 下栅极切口通道，上栅极比通道窄，并且可以在通道的相对端形成源极和漏极。 因此，可以减小源极 - 漏极电容和栅极 - 漏极电容，从而提高所产生的FET的速度。

公开(公告)号：US09029229B2

公开(公告)日：2015-05-12

申请号：US13904304

申请日：2013-05-29

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  Peng Cheng ,  Vibhor Jain ,  Vikas Kumar Kaushal ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L29/66242 ,  H01L29/7371

Abstract: Disclosed are devices and methods of forming the devices wherein pair(s) of first openings are formed through a dielectric layer and a first semiconductor layer into a substrate and, within the substrate, the first openings of each pair are expanded laterally and merged to form a corresponding trench. Dielectric material is deposited, filling the upper portions of the first openings and creating trench isolation region(s). A second semiconductor layer is deposited and second opening(s) are formed through the second semiconductor and dielectric layers, exposing monocrystalline portion(s) of the first semiconductor layer between the each pair of first openings. A third semiconductor layer is epitaxially deposited with a polycrystalline section on the second semiconductor layer and monocrystalline section(s) on the exposed monocrystalline portion(s) of the first semiconductor layer. A crystallization anneal is performed and a device (e.g., a bipolar device) is formed incorporating the resulting monocrystalline second and third semiconductor layers.

Abstract translation: 公开了形成器件的器件和方法，其中第一开口的一对通过电介质层形成，第一半导体层形成到衬底中，并且在衬底内，每对的第一开口横向膨胀并且形成 相应的沟槽。 沉积电介质材料，填充第一开口的上部并产生沟槽隔离区。 沉积第二半导体层，并且通过第二半导体和电介质层形成第二开口，使第一半导体层的单晶部分暴露在每对第一开口之间。 第三半导体层在第二半导体层上的多晶部分和第一半导体层的暴露的单晶部分上的单晶部分外延沉积。 进行结晶退火，并且形成结合所得单晶第二和第三半导体层的器件（例如，双极器件）。

公开(公告)号：US08957405B2

公开(公告)日：2015-02-17

申请号：US14076714

申请日：2013-11-11

Applicant: International Business Machines Corporation

Inventor： James W. Adkisson ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch

IPC: H01L21/00 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/1606 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/186 ,  H01L27/1222 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: Manufacturing a semiconductor structure including: forming a seed material on a sidewall of a mandrel; forming a graphene field effect transistor (FET) on the seed material; and removing the seed material.

Abstract translation: 制造半导体结构，包括：在心轴的侧壁上形成种子材料; 在种子材料上形成石墨烯场效应晶体管（FET）; 并移除种子材料。

公开(公告)号：US10277188B2

公开(公告)日：2019-04-30

申请号：US15971257

申请日：2018-05-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H03H9/54 ,  H03H3/02 ,  H03H3/08 ,  H03H3/007 ,  H03H9/56 ,  H03H9/10 ,  H03H9/24 ,  G06F17/50 ,  H03H9/02 ,  H03H9/64 ,  H03H9/15

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.

公开(公告)号：US09892958B2

公开(公告)日：2018-02-13

申请号：US14558037

申请日：2014-12-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Anthony K. Stamper

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/423 ,  H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L23/485 ,  H01L21/768 ,  H01L21/02 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/8249 ,  H01L23/485 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact via to a first portion of a first device. The method further includes filling the first contact via with metal material to form a first metal contact to the first portion of the first device. The method further includes forming additional contact vias to other portions of the first device and contacts of a second device. The method further includes cleaning the additional contact vias while protecting the first metal contact of the first portion of the first device. The method further includes filling the additional contact vias with metal material to form additional metal contacts to the other portions of the first device and the second device.