公开(公告)号：US12150393B2

公开(公告)日：2024-11-19

申请号：US17936982

申请日：2022-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Victor W. C. Chan ,  Jin Ping Han ,  Samuel Sung Shik Choi ,  Injo Ok

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

Abstract: An integrated circuit includes a field effect transistor (FET) and a phase change memory (PCM) cell. The PCM cell includes a heater, wherein a bottom surface of the heater is at or below a top surface of the FET.

公开(公告)号：US20240186386A1

公开(公告)日：2024-06-06

申请号：US18062552

申请日：2022-12-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin Ping Han ,  Jianshi Tang ,  Kevin K. Chan ,  Ahmet Serkan Ozcan

IPC: H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H10K10/46

CPC classification number: H01L29/408 ,  H01L29/401 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/7869 ,  H01L51/0525 ,  H01L51/0529

Abstract: A method of making a mobile ion regulated device includes stacking a dielectric layer on a substrate. Mobile ions are placed within the dielectric layer. An electrode layer is provided on the dielectric layer. The mobile ions are directed to a designated area of the dielectric layer.

公开(公告)号：US20230200267A1

公开(公告)日：2023-06-22

申请号：US18172385

申请日：2023-02-22

Applicant: International Business Machines Corporation

Inventor： Kevin W. Brew ,  Injo Ok ,  Jin Ping Han ,  Timothy Mathew Philip ,  Matthew Joseph BrightSky ,  Nicole Saulnier

IPC: G11C13/00 ,  G11C11/54

CPC classification number: H10N70/231 ,  G11C11/54 ,  H10N70/826 ,  H10B63/24 ,  G11C13/0004 ,  H10N70/8413 ,  G06N3/065 ,  G11C2213/72

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

公开(公告)号：US11621394B2

公开(公告)日：2023-04-04

申请号：US17136384

申请日：2020-12-29

Applicant: International Business Machines Corporation

Inventor： Kevin W. Brew ,  Injo Ok ,  Jin Ping Han ,  Timothy Mathew Philip ,  Matthew Joseph BrightSky ,  Nicole Saulnier

IPC: G11C11/00 ,  H01L45/00 ,  H01L27/24 ,  G11C11/54 ,  G11C13/00 ,  G06N3/063

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

公开(公告)号：US20220209105A1

公开(公告)日：2022-06-30

申请号：US17136384

申请日：2020-12-29

Applicant: International Business Machines Corporation

Inventor： Kevin W. Brew ,  Injo Ok ,  Jin Ping Han ,  Timothy Mathew Philip ,  Matthew Joseph BrightSky ,  Nicole Saulnier

IPC: H01L45/00 ,  H01L27/24 ,  G11C11/54 ,  G11C13/00

Abstract: A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

公开(公告)号：US10818333B2

公开(公告)日：2020-10-27

申请号：US16550809

申请日：2019-08-26

Applicant: International Business Machines Corporation

Inventor： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC: G11C11/22 ,  H03K19/1776 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C11/54 ,  G11C16/10 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G11C13/00

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US20200053299A1

公开(公告)日：2020-02-13

申请号：US16100249

申请日：2018-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Zhang ,  Jin Ping Han ,  Dennis M. Newns ,  Xiaodong Cui

IPC: H04N5/341 ,  H04N5/235 ,  H04N5/232 ,  H01L25/16

Abstract: According to one or more embodiments of the present invention, an image processing system includes a cross-point synapse array that includes multiple row wires, multiple column wires, and multiple cross-point devices, a cross-point device at each intersection of the row wires and the column wires. The image processing system further includes an image sensor array that includes multiple pixel unit circuits, each pixel unit circuit is connected to a corresponding row wire of the cross-point synapse array, wherein the pixel unit circuit generates a voltage output based on an input light. The image processing system further includes a pixel unit controller that adjusts an exposure time of the pixel unit circuits based on voltage outputs from the pixel unit circuits respectively.

公开(公告)号：US20190252499A1

公开(公告)日：2019-08-15

申请号：US16395024

申请日：2019-04-25

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L29/12 ,  H01L23/52 ,  H01L29/06 ,  H01L27/085

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US20190131383A1

公开(公告)日：2019-05-02

申请号：US15797848

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L49/02 ,  H01L27/11507 ,  H01B3/10 ,  H01L21/02 ,  H01L21/283 ,  H01L21/3213

CPC classification number: H01L28/40 ,  H01B3/10 ,  H01L21/02181 ,  H01L21/02356 ,  H01L21/283 ,  H01L21/32133 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

公开(公告)号：US09935174B2

公开(公告)日：2018-04-03

申请号：US15372519

申请日：2016-12-08

Applicant: International Business Machines Corporation

Inventor： Victor Chan ,  Jin Ping Han ,  Shangbin Ko

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/225 ,  H01L21/283 ,  H01L23/535

CPC classification number: H01L29/66545 ,  H01L21/2253 ,  H01L21/283 ,  H01L23/535 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/7845

Abstract: A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.