公开(公告)号：US20230093026A1

公开(公告)日：2023-03-23

申请号：US17479321

申请日：2021-09-20

Applicant: International Business Machines Corporation

Inventor： Timothy Mathew PHILIP ,  Anirban CHANDRA ,  Kevin W. BREW ,  Lawrence A. CLEVENGER

IPC: H01L45/00 ,  H01L27/24

Abstract: Insulated phase change memory devices are provided that include a first electrode; a second electrode; a phase change material disposed in an electrical path between the first electrode and the second electrode; and a porous dielectric configured to concentrate heat produced by a reset current carried through the phase change material between the first electrode and the second electrode to mitigate an amount of heat that escapes from the phase change material. The porous dielectric may be an inherently porous dielectric material or a dielectric material in which porous structures are induced during fabrication. Methods of fabrication of such devices are also provided.

公开(公告)号：US20200075406A1

公开(公告)日：2020-03-05

申请号：US16669708

申请日：2019-10-31

Applicant: international Business Machines Corporation

Inventor： Benjamin David Briggs ,  Lawrence A. CLEVENGER ,  Bartlet H. DEPROSPO ,  Michael RIZZOLO

IPC: H01L21/768 ,  H01L23/532 ,  B23K26/352 ,  B23K26/062 ,  B23K26/70 ,  B23K26/03 ,  B23K26/00 ,  B23K26/082 ,  H01L21/66 ,  H01L21/67

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

公开(公告)号：US20190164163A1

公开(公告)日：2019-05-30

申请号：US15827181

申请日：2017-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Spyridon SKORDAS ,  Lawrence A. CLEVENGER ,  Richard C. JOHNSON

IPC: G06Q20/40 ,  G06Q50/26

Abstract: Devices and methods for granting requests for authorization using data of devices associated with requestors are disclosed. A method includes: receiving, by a computing device, a request for authorization; receiving, by the computing device, identification information for at least one device of a requestor; determining, by the computing device, a risk score using the received identification information for the at least one device of the requestor; and in response to the risk score exceeding a predetermined threshold, the computing device granting the request for authorization.

公开(公告)号：US20190013244A1

公开(公告)日：2019-01-10

申请号：US16114816

申请日：2018-08-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo CHENG ,  Lawrence A. CLEVENGER ,  Balasubramanian S. PRANATHARTHIHARAN ,  John ZHANG

IPC: H01L21/8234 ,  H01L29/786 ,  H01L21/02 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06 ,  H01L27/088 ,  H01L21/306 ,  H01L29/78

Abstract: A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.

公开(公告)号：US20180197858A1

公开(公告)日：2018-07-12

申请号：US15402704

申请日：2017-01-10

Applicant: International Business Machines Corporation

Inventor： Lawrence A. CLEVENGER ,  Leigh Anne H. CLEVENGER ,  Mona A. EBRISH ,  Gauri KARVE ,  Fee Li LIE ,  Deepika PRIYADARSHINI ,  Indira Priyavarshini SESHADRI ,  Nicole A. SAULNIER

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8258 ,  H01L21/027 ,  H01L21/311 ,  H01L21/033 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/7849

Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

公开(公告)号：US20180005941A1

公开(公告)日：2018-01-04

申请号：US15199321

申请日：2016-06-30

Applicant: International Business Machines Corporation

Inventor： Benjamin David BRIGGS ,  Lawrence A. CLEVENGER ,  Bartlet H. DEPROSPO ,  Huai HUANG ,  Christopher J. PENNY ,  Michael RIZZOLO

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329

Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.

公开(公告)号：US20150194355A1

公开(公告)日：2015-07-09

申请号：US14147996

申请日：2014-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cyril CABRAL, Jr. ,  Lawrence A. CLEVENGER ,  John M. COHN ,  Jeffrey P. GAMBINO ,  William J. MURPHY ,  Anthony J. TELENSKY

IPC: H01L21/66 ,  G05B19/418 ,  H01L21/67

CPC classification number: G05B19/418 ,  C23C14/546 ,  G01B7/066 ,  G05B2219/2602 ,  H01L21/67253

Abstract: Systems and methods are provided for implementing a crystal oscillator to monitor and control semiconductor fabrication processes. More specifically, a method is provided for that includes performing at least one semiconductor fabrication process on a material of an integrated circuit (IC) disposed within a processing chamber. The method further includes monitoring by at least one electronic oscillator disposed within the processing chamber for the presence or absence of a predetermined substance generated by the at least one semiconductor fabrication process. The method further includes controlling the at least one semiconductor fabrication process based on the presence or absence of the predetermined substance detected by the at least one electronic oscillator.

Abstract translation: 提供了用于实现晶体振荡器以监测和控制半导体制造工艺的系统和方法。 更具体地，提供了一种方法，其包括对设置在处理室内的集成电路（IC）的材料进行至少一个半导体制造工艺。 该方法还包括由至少一个设置在处理室内的电子振荡器来监测是否存在由至少一个半导体制造工艺产生的预定物质。 该方法还包括基于由至少一个电子振荡器检测到的预定物质的存在或不存在来控制至少一个半导体制造过程。