公开(公告)号：US10168427B2

公开(公告)日：2019-01-01

申请号：US15962418

申请日：2018-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Li-Wen Hung ,  Reinaldo Vega

IPC: G01S15/04 ,  G01S15/02 ,  G01S15/12 ,  G06K7/10 ,  H04B11/00 ,  G01S15/74

Abstract: A system and method are provided. The system includes a data reader having a processor for performing a signal frequency analysis, an ultrasound transmitter for transmitting ultrasound signals, and an ultrasound receiver for receiving reflected ultrasound signals. The system further includes a movable reflector for receiving the ultrasound signals and reflecting the ultrasounds signals back to the ultrasound receiver (a) as the reflected ultrasound signals without modulation when the movable reflector is stationary and (b) as the reflected ultrasound signals with modulation when the movable reflector is mobile. The system also includes a chip for storing a specification of motion states for the movable reflector.

公开(公告)号：US20180308945A1

公开(公告)日：2018-10-25

申请号：US15975869

申请日：2018-05-10

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US10001561B2

公开(公告)日：2018-06-19

申请号：US15156061

申请日：2016-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Li-Wen Hung ,  Reinaldo Vega

IPC: G01S15/04 ,  G01S15/02 ,  G01S15/12 ,  G06K7/10

CPC classification number: G01S15/04 ,  G01S15/74 ,  H04B11/00

Abstract: A system and method are provided. The system includes a data reader having a processor for performing a signal frequency analysis, an ultrasound transmitter for transmitting ultrasound signals, and an ultrasound receiver for receiving reflected ultrasound signals. The system further includes a movable reflector for receiving the ultrasound signals and reflecting the ultrasounds signals back to the receiver (a) as the reflected ultrasound signals without modulation when the reflector is stationary and (b) as the reflected ultrasound signals with modulation when the reflector is mobile. The system also includes a chip for storing a specification of motion states for the reflector. The processor performs the signal frequency analysis to detect a presence or an absence of modulated frequency components in a received ultrasound signal and outputs a first value or a second value respectively depending upon whether the presence or the absence of the modulated frequency components is detected.

公开(公告)号：US20250133816A1

公开(公告)日：2025-04-24

申请号：US18489056

申请日：2023-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Kisik Choi ,  Shay Reboh ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

公开(公告)号：US12135497B2

公开(公告)日：2024-11-05

申请号：US17490454

申请日：2021-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Takashi Ando ,  Reinaldo Vega ,  Praneet Adusumilli

IPC: G03F1/36 ,  G03F1/38 ,  G03F1/92

Abstract: A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.

公开(公告)号：US12080714B2

公开(公告)日：2024-09-03

申请号：US17447944

申请日：2021-09-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Alexander Reznicek ,  Kangguo Cheng

IPC: H01L29/775 ,  H01L21/8234 ,  H01L23/538 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L27/092 ,  H01L21/823431 ,  H01L23/5386 ,  H01L27/1218 ,  H01L27/127

Abstract: An integrated circuit component includes a first layer including first and second areas of epitaxy material. The first layer has a first polarity. The component further includes a second layer including third and fourth areas of epitaxy material. The second layer has a second polarity that is different than the first polarity. The third area is arranged at least partially above the first area, and the fourth area is arranged at least partially above the second area. The integrated circuit component further includes an interconnect in direct contact with one of the first area and the third area and in direct contact with one of the second area and the fourth area. The interconnect has a top surface that does not extend substantially above an uppermost surface of the second layer.

公开(公告)号：US20240250136A1

公开(公告)日：2024-07-25

申请号：US18158505

申请日：2023-01-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor structure is presented including backside contacts with jumpers and frontside back-end-of-line (BEOL) components electrically connected to the backside contacts by one or more deep via contacts. The jumpers electrically connect a plurality of source/drain (S/D) regions. At least one of the backside contacts is electrically connected to a backside power rail. At least one of the backside contacts has a first height and at least one of the backside contacts has a second height, where the second height is greater than the first height.

公开(公告)号：US20240203880A1

公开(公告)日：2024-06-20

申请号：US18068123

申请日：2022-12-19

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  Reinaldo Vega

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L23/485 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655

Abstract: One or more systems, devices, and/or methods of use provided herein relate to a semiconductor device with separate power supplies for front side and backside stacked power distribution. A semiconductor device can include one or more circuits, a first power supply, a second power supply, and a third power supply. The first power supply can be disposed on a first side of the one or more circuits. The second power supply can be disposed on the first side of the one or more circuits. Further, the third power supply can be disposed on a second side of the one or more circuits. Additionally, the first side of the one or more circuits can be opposite to the second side of the one or more circuits.

公开(公告)号：US20240201583A1

公开(公告)日：2024-06-20

申请号：US18083851

申请日：2022-12-19

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Takashi Ando ,  Praneet Adusumilli ,  Reinaldo Vega ,  David Wolpert

IPC: G03F7/00 ,  G03F7/09 ,  G03F7/20 ,  G06K19/06

CPC classification number: G03F7/0005 ,  G03F7/09 ,  G03F7/2047 ,  G03F7/70325 ,  G06K19/06028 ,  G06K19/06037

Abstract: A system and method of leveraging sub-resolution assist feature (SRAF) to intentionally distort a feature of a pattern for identification and security purposes. A method of forming an identifier on a semiconductor structure includes: receiving, at a semiconductor manufacturing foundry, a specification of an identifier including a pattern comprising a combination of main features; designing a lithographic mask structure based on the received identifier specification, the lithographic mask structure including mask features corresponding to the specified main features and at least one sub-resolution assist feature (SRAF) structure in a geometrical relationship with a corresponding mask feature for forming, using a lithography process, a uniquely modified identifier pattern comprising a combination of modified main features; and then subsequently lithographically exposing, employing the mask structure, photoresist layers at an optical condition and subsequently developing the photoresist layers to transfer the uniquely modified identifier pattern to a surface of a semiconductor wafer.

公开(公告)号：US20240186177A1

公开(公告)日：2024-06-06

申请号：US18060986

申请日：2022-12-02

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Reinaldo Vega ,  Takashi Ando ,  David Wolpert

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a skip via. The skip via includes a first skip via segment vertically connected to a second skip via segment. The first skip via segment has a first width and the second skip via segment has a second width.