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    PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE
    21.
    发明申请
    PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20220367385A1

    公开(公告)日：2022-11-17

    申请号：US17547200

    申请日：2021-12-09

    Applicant: Industrial Technology Research Institute

    Inventor： Yu-Min Lin ,  Ching-Kuan Lee ,  Chao-Jung Chen ,  Ren-Shin Cheng ,  Ang-Ying Lin ,  Po-Chih Chang

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/15 ,  H01L21/48 ,  H01L21/56

    Abstract: A package carrier, including a first redistribution structure layer, multiple conductive connecting members, a connection structure layer, at least one stiffener, and a molding compound, is provided. The conductive connecting members are disposed on a first surface of the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The connection structure layer is disposed on a second surface of the first redistribution structure layer and includes a substrate and multiple pads. A top surface and a bottom surface of each pad are respectively exposed to an upper surface and a lower surface of the substrate. The pads are electrically connected to the first redistribution structure layer. The stiffener is disposed on the first surface and is located at least between the conductive connecting members. The molding compound is disposed on the first surface and covers the conductive connecting members and the stiffener.

    IMAGE SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF
    22.
    发明申请
    IMAGE SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220130812A1

    公开(公告)日：2022-04-28

    申请号：US17568740

    申请日：2022-01-05

    Applicant: Industrial Technology Research Institute

    Inventor： Sheng-Tsai Wu ,  Yu-Min Lin ,  Yuan-Yin Lo ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Chao-Jung Chen ,  Shin-Yi Huang

    IPC: H01L25/18 ,  H01L23/00 ,  H01L31/0203

    Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

    Image sensor package and manufacturing method thereof
    23.
    发明授权
    Image sensor package and manufacturing method thereof 有权

    公开(公告)号：US11251174B2

    公开(公告)日：2022-02-15

    申请号：US16884051

    申请日：2020-05-27

    Applicant: Industrial Technology Research Institute

    Inventor： Sheng-Tsai Wu ,  Yu-Min Lin ,  Yuan-Yin Lo ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Chao-Jung Chen ,  Shin-Yi Huang

    IPC: H01L31/0203 ,  H01L25/18 ,  H01L23/00

    Abstract: An image sensor package and a manufacturing method thereof are provided. The image sensor package includes a redistribution circuit structure; an image sensing chip disposed on the redistribution circuit structure and having a sensing surface, on which a sensing area and a first conductive pillar arranged in the periphery of the sensing area are disposed; a lid covering the sensing area; an encapsulant disposed on the redistribution circuit structure and encapsulating at least part of the image sensing chip and the cover; and a top tier semiconductor chip disposed above the image sensing chip and having an active surface on which a first conductor is disposed. The first conductor overlaps the image sensing chip in a direction perpendicular to the sensing surface. The first conductive pillar and the first conductor are aligned and bonded to each other to electrically connect the image sensing chip and the top tier semiconductor chip.

    Chip package structure
    24.
    发明授权
    Chip package structure 有权

    公开(公告)号：US11239168B2

    公开(公告)日：2022-02-01

    申请号：US16849999

    申请日：2020-04-16

    Applicant: Industrial Technology Research Institute

    Inventor： Hsin-Han Lin ,  Yu-Min Lin ,  Tao-Chih Chang

    IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L25/065

    Abstract: A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.

    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE
    25.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210082810A1

    公开(公告)日：2021-03-18

    申请号：US17095744

    申请日：2020-11-12

    Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

    Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Tao-Chih Chang ,  Yu-Min Lin ,  Sheng-Tsai Wu

    IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/04

    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

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