公开(公告)号：US20160132269A1

公开(公告)日：2016-05-12

申请号：US14995145

申请日：2016-01-13

Applicant: INTEL CORPORATION

Inventor： Bill NALE

IPC: G06F3/06

Abstract: Provided are a method and apparatus for setting high address bits in a memory module. A memory module controller in the memory module, having pins to communicate on a bus, determines whether high address bits are available for the memory module, uses a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determine that the high address bits are not available to address a first address space in the memory module, and uses values communicated from the host memory controller on at least one of the pins used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space.

Abstract translation: 提供了一种用于设置存储器模块中的高地址位的方法和装置。 存储器模块中的存储器模块控制器具有用于在总线上通信的引脚，确定高地址位是否可用于存储器模块，对于至少一个高地址位使用预定值，响应地从主机存储器控制器传送地址 以确定高地址位不可用于寻址存储器模块中的第一地址空间，并且响应于确定所述至少一个高地址位的至少一个引脚使用从主机存储器控制器传送的值 高地址位可用于寻址第二地址空间，其中第二地址空间大于第一地址空间。

公开(公告)号：US20160098366A1

公开(公告)日：2016-04-07

申请号：US14967226

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  John V. LOVELACE ,  Murugasamy M. NACHIMUTHU ,  Tuan M. QUACH

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates one of the mode registers and includes data for the indicated mode register

Abstract translation: 提供了一种用于对存储器模块中的寄存器进行编码的方法和装置的方法和装置。 通过总线将模式寄存器命令发送到存储器模块，在对存储器模块的总线进行总线操作的训练之前对存储器模块的初始化进行编程，以对存储器模块中的多个模式寄存器中的一个进行编程，其中模式寄存器 命令指示模式寄存器之一，并包括指示模式寄存器的数据

公开(公告)号：US20230071117A1

公开(公告)日：2023-03-09

申请号：US17987687

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Hussein ALAMEER ,  Bill NALE ,  George VERGIS ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A memory module has a registering clock driver (RCD) that issues two column address strobe (CAS) commands with a single memory access command to exchange a double amount of data per dynamic random access memory (DRAM) device per memory access command. With double the amount of data per DRAM device, the memory module can provide double the pseudo channels as compared to a memory module where a single CAS command is issued per access command. The RCD can time division multiplex separate first commands for a first group of the DRAM devices from second commands for a second group of the DRAM devices on the command/address (CA) bus.

公开(公告)号：US20220262428A1

公开(公告)日：2022-08-18

申请号：US17738923

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Jongwon LEE ,  Tomer LEVY ,  Bill NALE ,  Amir Ali RADJAI

IPC: G11C11/406 ,  G11C11/4078 ,  G11C11/4096

Abstract: Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and/or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT_n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and/or recovery.

公开(公告)号：US20220229790A1

公开(公告)日：2022-07-21

申请号：US17710813

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Bill NALE

IPC: G06F13/16 ,  G06F13/40

Abstract: A memory module has data buffers coupled to a registered clock driver (RCD) via buffer communication (BCOM) bus. The memory module includes memory devices managed as a first pseudo channel and a second pseudo channel. The data buffers manage data transmission between the memory devices and a host based on commands received over the BCOM bus. The RCD can send a first BCOM command on the BCOM bus to the data buffer, the first BCOM command to specify a rank and a burst length for the first pseudo channel. The RCD can send a second BCOM command on the BCOM bus to the data buffer, the second BCOM command to specify a rank and a burst length for the second pseudo channel, and a timing offset relative to the first BCOM command.

公开(公告)号：US20210279128A1

公开(公告)日：2021-09-09

申请号：US17327432

申请日：2021-05-21

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Bill NALE ,  Zibing YANG ,  Yanjie ZHU

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30

Abstract: A method is described. The method includes a buffer semiconductor chip receiving a plurality of data signals. The method includes the buffer chip calculating first CRC information from the plurality of data signals. The method includes the buffer chip transmitting the plurality of data signals in parallel with the first CRC information if a read burst transfer sequence is being performed, the buffer chip receiving second CRC information in parallel with the plurality of data signals and comparing the first CRC information with the second CRC information if a write burst transfer sequence is being performed.

公开(公告)号：US20210151095A1

公开(公告)日：2021-05-20

申请号：US17157826

申请日：2021-01-25

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US20210151083A1

公开(公告)日：2021-05-20

申请号：US17133484

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Aiswarya M. PIOUS ,  Raji JAMES ,  Phani K. ALAPARTHI ,  George VERGIS ,  Bill NALE ,  Konika GANGULY

IPC: G11C5/14

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

公开(公告)号：US20190043557A1

公开(公告)日：2019-02-07

申请号：US16001869

申请日：2018-06-06

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Bill NALE

IPC: G11C11/406 ,  G06F3/06 ,  G11C7/10

Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

公开(公告)号：US20190042500A1

公开(公告)日：2019-02-07

申请号：US16017515

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Bill NALE ,  Chong J. ZHAO ,  James A. McCALL ,  George VERGIS

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to multiplex write data to different groups of memory chips on the DIMM during a same burst write sequence.