公开(公告)号：US20190198627A1

公开(公告)日：2019-06-27

申请号：US16326846

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  PAUL B. FISCHER

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/20 ,  H01L29/778 ,  H01L21/768 ,  H01L29/423

CPC classification number: H01L29/41766 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/735 ,  H01L29/7786

Abstract: Integrated circuit transistor structures are provided that may reduce capacitive parasitics by using metal on both sides (top and bottom) of a given integrated circuit transistor device layer. For example, in an embodiment, the drain metal interconnect is provided above the transistor device layer, and the source metal interconnect is provided below the transistor layer. Such a configuration reduces the parasitic capacitance not only between the source and drain metal interconnect layers, but also between the neighboring conductors of the drain metal interconnect layer, because the number of pass-thru conductors in the drain metal interconnect layer to access an upper conductor in the source metal interconnect layer is reduced. In other embodiments, the source metal interconnect remains above the transistor device layer, and the drain metal interconnect is moved to below the transistor device layer, to provide similar benefits. Techniques apply equally to any transistor type, including FETs and BJTs.

公开(公告)号：US20190189771A1

公开(公告)日：2019-06-20

申请号：US16322816

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  PAUL B. FISCHER

IPC: H01L29/66 ,  H01L29/872 ,  H01L29/06 ,  H01L21/762 ,  H01L29/20 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L29/66212 ,  H01L21/76224 ,  H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/872

Abstract: Techniques are disclosed for forming Schottky diodes on semipolar planes of group III-nitride (III-N) material structures. A lateral epitaxial overgrowth (LEO) scheme may be used to form the group III-N material structures upon which Schottky diodes can then be formed. The LEO scheme for forming III-N structures may include forming shallow trench isolation (STI) material on a semiconductor substrate, patterning openings in the STI, and growing the III-N material on the semiconductor substrate to form structures that extend through and above the STI openings, for example. A III-N structure may be formed using only a single STI opening, where such a III-N structure may have a triangular prism-like shape above the top plane of the STI layer. Further processing can include forming the gate (e.g., Schottky gate) and tied together source/drain regions on semipolar planes (or sidewalls) of the III-N structure to form a two terminal Schottky diode.

公开(公告)号：US20190088759A1

公开(公告)日：2019-03-21

申请号：US16080824

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： SEUNG HOON SUNG ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H01L29/49 ,  H01L29/423

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66606 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7856

Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

公开(公告)号：US20180170747A1

公开(公告)日：2018-06-21

申请号：US15576510

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  SANAZ K. GARDNER ,  RAVI PILLARISETTY ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  ROBERT S. CHAU

IPC: B81C1/00 ,  B81B7/02 ,  B81B3/00

CPC classification number: B81C1/00246 ,  B81B3/0021 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C2203/0714 ,  G01L1/18

Abstract: Techniques are disclosed for forming group III material-nitride (III-N) microelectromechanical systems (MEMS) structures on a group IV substrate, such as a silicon, silicon germanium, or germanium substrate. In some cases, the techniques include forming a III-N layer on the substrate and optionally on shallow trench isolation (STI) material, and then releasing the III-N layer by etching to form a free portion of the III-N layer suspended over the substrate. The techniques may include, for example, using a wet etch process that selectively etches the substrate and/or STI material, but does not etch the III-N material (or etches the III-N material at a substantially slower rate). Piezoresistive elements can be formed on the III-N layer to, for example, detect vibrations or deflection in the free/suspended portion of the III-N layer. Accordingly, MEMS sensors can be formed using the techniques, such as accelerometers, gyroscopes, and pressure sensors, for example.

公开(公告)号：US20160365416A1

公开(公告)日：2016-12-15

申请号：US15120803

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  WILLY RACHMADY ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  RAVI PILLARISETTY ,  ROBERT S. CHAU

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

Abstract translation: 实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。 另一实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。 本文还包括其它实施例。

公开(公告)号：US20160204246A1

公开(公告)日：2016-07-14

申请号：US14914102

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

Abstract translation: 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

公开(公告)号：US20160190319A1

公开(公告)日：2016-06-30

申请号：US14912059

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： JACK T. KAVALIEROS ,  MARKO RADOSAVLJEVIC ,  MATTHEW V. METZ ,  HAN WUI THEN ,  BENJAMIN CHU-KUNG ,  VAN H. LE ,  NILOY MUKHERJEE ,  SANSAPTAK DASGUPTA ,  RAVI PILLARISETTY ,  GILBERT DEWEY ,  ROBERT S. CHAU ,  NANCY M. ZELICK ,  WILLY RACHMADY

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/267 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a lower portion composed of a first semiconductor material with a first lattice constant (L1), and has an upper portion composed of a second semiconductor material with a second lattice constant (L2). A cladding layer is disposed on the upper portion, but not on the lower portion, of the semiconductor fin. The cladding layer is composed of a third semiconductor material with a third lattice constant (L3), wherein L3>L2>L1. A gate stack is disposed on a channel region of the cladding layer. Source/drain regions are disposed on either side of the channel region.

Abstract translation: 描述了具有多层柔性衬底的非平面半导体器件以及制造这种非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍具有由具有第一晶格常数（L1）的第一半导体材料构成的下部，并且具有由具有第二晶格常数（L2）的第二半导体材料构成的上部。 在半导体翅片的上部而不是下部设置包覆层。 包覆层由具有第三晶格常数（L3）的第三半导体材料构成，其中L3> L2> L1。 栅堆叠设置在包层的沟道区上。 源极/漏极区域设置在沟道区域的两侧。

公开(公告)号：US20210118983A1

公开(公告)日：2021-04-22

申请号：US17116297

申请日：2020-12-09

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H01L49/02 ,  H01L23/522

Abstract: Techniques are disclosed for forming an integrated circuit including a capacitor having a multilayer dielectric stack. For example, the capacitor may be a metal-insulator-metal capacitor (MIMcap), where the stack of dielectric layers is used for the insulator or ‘I’ portion of the MIM structure. In some cases, the composite or multilayer stack for the insulator portion of the MIM structure may include a first oxide layer, a dielectric layer, a second oxide layer, and a high-k dielectric layer, as will be apparent in light of this disclosure. Further, the multilayer dielectric stack may include an additional high-k dielectric layer, for example. Use of such multilayer dielectric stacks can enable increases in capacitance density and/or breakdown voltage for a MIMcap device. Further, use of a multilayer dielectric stack can enable tuning of the breakdown and capacitance characteristics as desired. Other embodiments may be described and/or disclosed.

公开(公告)号：US20200373403A1

公开(公告)日：2020-11-26

申请号：US16990219

申请日：2020-08-11

Applicant: INTEL CORPORATION

Inventor： SEUNG HOON SUNG ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

公开(公告)号：US20200321445A1

公开(公告)日：2020-10-08

申请号：US16907445

申请日：2020-06-22

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/778 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on−VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi −Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including HfxZryO) can be formed between a transistor gate dielectric layer and gate electrode to achieve such benefits.