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    MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION
    21.
    发明申请
    MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION 有权

    公开(公告)号：US20210103682A1

    公开(公告)日：2021-04-08

    申请号：US17020486

    申请日：2020-09-14

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Siddhartha Chhabra ,  Nadav Bonen

    IPC: G06F21/79 ,  G06F21/75 ,  G06F21/76 ,  G06F12/14

    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.

    Programmable on-die termination timing in a multi-rank system
    22.
    发明授权
    Programmable on-die termination timing in a multi-rank system 有权

    公开(公告)号：US10680613B2

    公开(公告)日：2020-06-09

    申请号：US16146326

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Kuljit S. Bains ,  Alexey Kostinsky ,  Nadav Bonen

    IPC: H03K19/0175 ,  G06F3/06 ,  G06F13/16

    Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

    MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION
    23.
    发明申请
    MULTI-TENANT CRYPTOGRAPHIC MEMORY ISOLATION 审中-公开

    公开(公告)号：US20190102577A1

    公开(公告)日：2019-04-04

    申请号：US15720360

    申请日：2017-09-29

    Applicant: Intel Corporation

    Inventor： Shay Gueron ,  Siddhartha Chhabra ,  Nadav Bonen

    IPC: G06F21/79 ,  G06F21/76 ,  G06F21/75

    Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.

    Avoiding DQS false sampling triggers
    26.
    发明授权
    Avoiding DQS false sampling triggers 有权

    公开(公告)号：US09640277B2

    公开(公告)日：2017-05-02

    申请号：US14142812

    申请日：2013-12-28

    Applicant: Intel Corporation

    Inventor： Nadav Bonen ,  Alexey Kostinsky

    IPC: G06F13/42 ,  G11C5/00 ,  G11C29/02 ,  G11C7/02 ,  G11C7/22

    CPC classification number: G11C29/022 ,  G11C7/02 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: A system avoids false sampling due to reflections from previous commands or other noise on a data strobe line. The system uses a normalizer circuit or leaker circuit, and the data strobe line is not optimally terminated or is unterminated. The data strobe line is to receive a burst of data sample pulses or edges and sample a data line based on the edges. The receiving device includes logic that generates a count triggered from an initial edge on the data strobe line, and identifies, based on the count, an initial valid edge of the burst. Any false strobes due to noise or reflections that are received prior to the actual burst can be rejected.

    SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFRESH ALGORITHM
    27.
    发明公开
    SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFRESH ALGORITHM 审中-公开

    公开(公告)号：US20240202124A1

    公开(公告)日：2024-06-20

    申请号：US18067779

    申请日：2022-12-19

    Applicant: Intel Corporation

    Inventor： Israel Diamand ,  Randy Osborne ,  Nadav Bonen

    IPC: G06F12/0831 ,  G06F12/0864

    CPC classification number: G06F12/0831 ,  G06F12/0864

    Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to computing systems implementing a very large cache for one or more processing engines in a shared memory system. According to various embodiments, a snoop filter tracks a hash value of the cached addresses instead of tracking the addresses themselves. Tracking hash values introduces inaccuracy and an inability to easily clean or refresh the snoop filter. A refresh algorithm maintains cache coherency without significant performance degradation. The cache refresh algorithm keeps the accuracy of the snoop filter, hence reducing the latency and power effects of false snoops. Further, the use of hash values reduces the hardware cost over traditional snoop filters.

    MEMORY MANAGEMENT TO IMPROVE POWER PERFORMANCE
    28.
    发明申请
    MEMORY MANAGEMENT TO IMPROVE POWER PERFORMANCE 有权

    公开(公告)号：US20210405892A1

    公开(公告)日：2021-12-30

    申请号：US17116991

    申请日：2020-12-09

    Applicant: Intel Corporation

    Inventor： Nadav Bonen ,  Sridhar Muthrasanallur ,  Srinivas Pandruvada ,  Vishwanath Somayaji ,  Prashant Kodali

    IPC: G06F3/06

    Abstract: Logical memory is divided into two regions. Data in the first region is always retained. The first region of memory is designated online (or powered on) and is not offlined during standby or low power mode. The second region is the rest of the memory which can be potentially placed in non-self-refresh mode during standby by offlining the memory region. Content in the second region can be moved to the first region or can be flushed to another memory managed by the operating system. When the first region does not have enough space to accommodate data from the second region, the operating system can increase the logical size of the first region. Retaining the content of the first region by putting that region in self-refresh and saving power in the second region by not putting it in self-refresh is performed by an improved Partial Array Self Refresh scheme.

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