公开(公告)号：US20160204263A1

公开(公告)日：2016-07-14

申请号：US14914906

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Jack T. KAVALIEROS ,  Ravi PILLARISETTY ,  Niti GOEL ,  Van H. LE ,  Gilbert DEWEY ,  Benjamin CHU-KUNG

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

Abstract translation: 一种包括半导体本体的装置，包括沟道区和设置在沟道区的相对侧上的结区，所述半导体本体包括包括第一带隙的第一材料; 以及包括第二材料的多个纳米线，所述第二材料包括不同于所述第一带隙的第二带隙，所述多个纳米线设置在穿过所述第一材料的分开的平面中，使得所述第一材料围绕所述多个纳米线中的每一个; 以及设置在通道区域上的栅极堆叠。 一种方法，包括在衬底上方的分开的平面中形成多个纳米线，所述多个纳米线中的每一个包括包括第一带隙的材料; 在所述多个纳米线的每一个周围分别形成包层材料，所述包层材料包括第二带隙; 聚结包层材料; 并在所述包层材料上设置栅极叠层。

公开(公告)号：US20220165737A1

公开(公告)日：2022-05-26

申请号：US17667498

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Van H. LE ,  Gilbert DEWEY ,  Abhishek A. SHARMA

IPC: H01L27/108

Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.

公开(公告)号：US20200235162A1

公开(公告)日：2020-07-23

申请号：US16632065

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20200168636A1

公开(公告)日：2020-05-28

申请号：US16631811

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Elijah V. KARPOV

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78

Abstract: Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the In topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type.

公开(公告)号：US20200161473A1

公开(公告)日：2020-05-21

申请号：US16633094

申请日：2017-09-17

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Willy RACHMADY ,  Brian S. DOYLE ,  Abhishek A. SHARMA ,  Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.

公开(公告)号：US20190244936A1

公开(公告)日：2019-08-08

申请号：US16386200

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Valluri RAO ,  Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Jack KAVALIEROS

IPC: H01L25/07 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/78 ,  H01L21/8258 ,  H01L29/778 ,  H01L25/00 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

公开(公告)号：US20190214559A1

公开(公告)日：2019-07-11

申请号：US16099173

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： James S. CLARKE ,  Ravi PILLARISETTY ,  Uday SHAH ,  Tejaswi K. INDUKURI ,  Niloy MUKHERJEE ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  G11C13/0007 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/1625 ,  H01L45/1633 ,  H01L45/1675

Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.

公开(公告)号：US20190165106A1

公开(公告)日：2019-05-30

申请号：US16246356

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/15 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/20 ,  H01L29/06 ,  H01L29/04 ,  H01L23/66 ,  H01L29/78 ,  H01L29/205 ,  H01L27/06

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20190066779A1

公开(公告)日：2019-02-28

申请号：US16080922

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Niloy MUKHERJEE ,  Uday SHAH

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/15 ,  G11C2213/53 ,  G11C2213/73 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2445

Abstract: One embodiment provides an apparatus. The apparatus includes a bipolar junction transistor (BJT) and an integrated resistive element. The BJT includes a base contact, a base region, a collector contact, a collector region and an integrated emitter contact. The integrated resistive element includes a resistive layer and an integrated electrode. The resistive element is positioned between the base region and the integrated emitter contact.

公开(公告)号：US20180374940A1

公开(公告)日：2018-12-27

申请号：US16110458

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Matthew V. METZ

IPC: H01L29/775 ,  H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/205 ,  H01L29/15 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/51 ,  B82Y40/00 ,  H01L29/06

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/155 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66469 ,  H01L29/78681 ,  H01L29/78696

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.