公开(公告)号：US09418888B2

公开(公告)日：2016-08-16

申请号：US14778562

申请日：2013-06-27

申请人： Intel Corporation

发明人： Robert L. Bristol ,  Rami Hourani ,  Eungnak Han ,  James M. Blackwell

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

摘要翻译： 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基底的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

公开(公告)号：US11373900B2

公开(公告)日：2022-06-28

申请号：US17025087

申请日：2020-09-18

申请人： Intel Corporation

发明人： Kevin Lin ,  Robert L. Bristol ,  Richard E. Schenker

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L23/528

摘要： Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US11315798B2

公开(公告)日：2022-04-26

申请号：US16075555

申请日：2016-04-08

申请人： Intel Corporation

发明人： Robert L. Bristol ,  Marie Krysak ,  James M. Blackwell ,  Florian Gstrein ,  Kent N. Frasure

IPC分类号： G03F7/039 ,  H01L21/311 ,  G03F7/004 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768

摘要： Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US11189790B2

公开(公告)日：2021-11-30

申请号：US16320789

申请日：2016-09-30

申请人： Intel Corporation

发明人： Kevin L. Lin ,  Sarah E. Atanasov ,  Kevin P. O'Brien ,  Robert L. Bristol

IPC分类号： H01L45/00 ,  H01L27/24

摘要： Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

公开(公告)号：US10804141B2

公开(公告)日：2020-10-13

申请号：US16092722

申请日：2016-05-27

申请人： Intel Corporation

发明人： Kevin Lin ,  Robert L. Bristol ,  Richard E. Schenker

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L23/528

摘要： Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US10457548B2

公开(公告)日：2019-10-29

申请号：US15573342

申请日：2015-06-22

申请人： Intel Corporation

发明人： Kevin Lai Lin ,  Chytra Pawashe ,  Raseong Kim ,  Ian A. Young ,  Kanwal Jit Singh ,  Robert L. Bristol

IPC分类号： B81B7/00 ,  B81C1/00 ,  H01L21/768

摘要： A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

公开(公告)号：US20190229189A1

公开(公告)日：2019-07-25

申请号：US16317023

申请日：2016-08-10

申请人： Intel Corporation

发明人： James S. Clarke ,  Robert L. Bristol ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Hubert C. George ,  Nicole K. Thomas

IPC分类号： H01L29/12 ,  H01L29/82 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/778

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.

公开(公告)号：US09443922B2

公开(公告)日：2016-09-13

申请号：US14622157

申请日：2015-02-13

申请人： INTEL CORPORATION

发明人： Mauro J. Kobrinsky ,  Robert L. Bristol ,  Michael C. Mayberry

IPC分类号： H01L21/20 ,  H01L49/02 ,  H01L27/22 ,  H01L21/033

CPC分类号： H01L28/60 ,  H01L21/0337 ,  H01L27/224 ,  H01L28/82

摘要： Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.

公开(公告)号：US20160190060A1

公开(公告)日：2016-06-30

申请号：US14909736

申请日：2013-09-27

申请人： Rami HOURANI ,  INTEL CORPORATION

发明人： Robert L. Bristol ,  James M. BLACKWELL ,  Scott B. CLENDENNING ,  Florian GSTREIN ,  Eungnak HAN ,  Grant M. KLOSTER ,  Jeanette M. ROBERTS ,  Patricio E. ROMERO ,  Rami HOURANI

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/3105

CPC分类号： H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

摘要翻译： 一个方面的方法包括通过通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

公开(公告)号：US08993404B2

公开(公告)日：2015-03-31

申请号：US13748277

申请日：2013-01-23

申请人： Intel Corporation

发明人： Mauro J. Kobrinsky ,  Robert L. Bristol ,  Michael C. Mayberry

IPC分类号： H01L21/20 ,  H01L21/033 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L21/0337 ,  H01L27/224 ,  H01L28/82

摘要： Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.

摘要翻译： 公开了用于提供具有大体波形轮廓的MIM电容器的技术和结构。 使用牺牲性自组织材料提供波纹形状，其有效地产生响应于被形成MIM电容器的介电材料的处理（热或其它合适的刺激）的图案。 自组织材料可以是例如响应于热或其它刺激而分离成两个交替相的定向自组装材料层，其中相中的一个相可以相对于另一相被选择性地蚀刻到 提供所需的图案。 在另一个例子中，自组织材料是在加热时聚结成孤岛的材料层。 根据本公开将会理解，所公开的技术可以用于例如增加每单位面积的电容，其可以通过蚀刻更深的电容器沟槽/孔来缩放。