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公开(公告)号：US12028191B2
公开(公告)日：2024-07-02
申请号：US17951562
申请日：2022-09-23
Applicant: Intel Corporation
Inventor： Yikui Dong , Shenggao Li
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03019
Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.
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公开(公告)号：US20230019127A1
公开(公告)日：2023-01-19
申请号：US17951562
申请日：2022-09-23
Applicant: Intel Corporation
Inventor： Yikui Dong , Shenggao Li
IPC: H04L25/03
Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.
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公开(公告)号：US20220191069A1
公开(公告)日：2022-06-16
申请号：US17119684
申请日：2020-12-11
Applicant: Intel Corporation
Inventor： Yikui Dong , Shenggao Li
IPC: H04L25/03
Abstract: Some embodiments include apparatus having multiple samplers in a decision feedback equalizer (DFE). The multiple samplers include at least two samplers and are configured to be activated in a first mode of the DFE to receive first input information from a summing circuit. At least one of the samplers is configured to be deactivated in a second mode of the DFE. At least one of the samplers is configured to be activated in the second mode of the DFE to receive second input information from the summing circuit.
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公开(公告)号：US10594326B2
公开(公告)日：2020-03-17
申请号：US15583835
申请日：2017-05-01
Applicant: Intel Corporation
Inventor： Shenggao Li
Abstract: Automatic digital sensing and compensation of frequency drift caused by temperature, aging, and/or other effects may be provided by including a compensation capacitor array and a sensing logic. The sensing logic may be configured to detect a drift in a first control signal and to provide the compensation capacitor array with a second control signal. The second control signal is configured to cause an adjustment of capacitance in the compensation capacitor array based on the detected drift in the first control signal.
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公开(公告)号：US20180375520A1
公开(公告)日：2018-12-27
申请号：US15991584
申请日：2018-05-29
Applicant: Intel Corporation
Inventor： Wenyan Vivian Jia , Shenggao Li , Fulvio Spagna
CPC classification number: H03L7/087 , G04F10/005 , H03D13/00
Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
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Patent Agency Ranking
公开(公告)号：US10063253B1
公开(公告)日：2018-08-28
申请号：US15629959
申请日：2017-06-22
Applicant: Intel Corporation
Inventor： Xiaoqing Wang , Shenggao Li
CPC classification number: H03M3/452 , G06G7/14 , G06G7/1865 , H03M3/424 , H04L25/0292 , H04L25/03006 , H04L25/03012
Abstract: Some embodiments include apparatuses having a first circuit portion, a second circuit portion, and a third circuit portion. The first circuit portion includes a first transistor to receive a first signal of a differential signal pair and a second transistor to receive a second signal of the differential signal pair. The second circuit portion is coupled to the first and second transistors and a first supply node, the second circuit portion including a first output node and a second output node to provide an output signal pair based on the differential signal pair. The third circuit portion includes a first diode-connected transistor coupled between the first output node and a second supply node and a second diode-connected transistor coupled between the second output node and the second supply node.
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27.发明申请APPARATUS AND METHOD FOR CLOCK SYNCHRONIZATION FOR INTER-DIE SYNCHRONIZED DATA TRANSFER 审中-公开用于内部同步数据传输的时钟同步的装置和方法公开(公告)号：US20170019112A1
公开(公告)日：2017-01-19
申请号：US15214364
申请日：2016-07-19
Applicant: Intel Corporation
Inventor： Shenggao Li , Stefan Rusu
CPC classification number: H03L7/00 , G06F1/12 , G06F13/4027 , H01L23/481 , H01L25/0657 , H01L2224/48137 , H01L2224/49175 , H01L2225/06541 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0012 , H04L7/0025 , Y02D10/14 , Y02D10/151
Abstract: Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.
Abstract translation: 描述了一种用于时钟同步的装置。 该装置包括一对互连; 包括具有耦合到所述互连中的一个的输出的第一相位内插器的第一管芯; 以及第二管芯，其中所述一对互连件将所述第一管芯连接到所述第二管芯。
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公开(公告)号：US09215104B1
公开(公告)日：2015-12-15
申请号：US14498025
申请日：2014-09-26
Applicant: INTEL CORPORATION
Inventor： Michael De Vita , Shenggao Li
CPC classification number: H04L25/03057 , H04L2025/03579 , H04L2025/03585
Abstract: Described are apparatuses and methods for generating floating taps for decision feedback equalizers. An apparatus may include a first delay cell including a first group of binary weighted sets of flip-flops to output a first signal, and a second delay cell including a second group of binary weighted sets of flip-flops to output a second signal. The apparatus may further include a multiplexer coupled to the first delay cell and the second delay cell to output a tap signal based on the first signal and the second signal. Other embodiments may be described and/or claimed.
Abstract translation: 描述了用于产生用于判决反馈均衡器的浮动抽头的装置和方法。 装置可以包括第一延迟单元，其包括第一组二进制加权的触发器组以输出第一信号;以及第二延迟单元，包括第二组二进制加权的触发器组，以输出第二信号。 该装置还可以包括耦合到第一延迟单元和第二延迟单元的多路复用器，以基于第一信号和第二信号输出抽头信号。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US10708093B2
公开(公告)日：2020-07-07
申请号：US16112391
申请日：2018-08-24
Applicant: Intel Corporation
Inventor： Shenggao Li , Ji Chen
Abstract: Some embodiments include apparatus and methods using a first latch in a decision feedback equalizer (DFE), a second latch in the DFE, and circuitry coupled to the first and second latches. The second latch includes a first input node coupled to an output node of the first latch. The circuitry includes a first input node coupled to the first output node, a second input node coupled to a second output node of the second latch, and an output node to provide information having a first output value based on first values of information at the first and second output nodes and a second output value based on second values of information at the first and second output nodes.
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公开(公告)号：US09985637B2
公开(公告)日：2018-05-29
申请号：US15391585
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Wenyan Vivian Jia , Shenggao Li , Fulvio Spagna
CPC classification number: H03L7/087 , G04F10/005 , H03D13/00
Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
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