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公开(公告)号：US20200251411A1
公开(公告)日：2020-08-06
申请号：US16855629
申请日：2020-04-22
Applicant: Intel Corporation
Inventor： Sanka Ganesan , William James Lambert , Zhichao Zhang , Sri Chaitra Jyotsna Chavali , Stephen Andrew Smith , Michael James Hill , Zhenguo Jiang
IPC: H01L23/498 , H01L21/56 , H05K7/02 , H01L25/065 , H01L25/10 , H01L23/00 , H05K1/18 , H01L21/48 , H01L23/31
Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
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公开(公告)号：US20200006866A1
公开(公告)日：2020-01-02
申请号：US16021474
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Sri Chaitra Jyotsna Chavali , Sanka Ganesan , William J. Lambert , Debendra Mallik , Zhichao Zhang
Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.
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公开(公告)号：US10424561B2
公开(公告)日：2019-09-24
申请号：US15863821
申请日：2018-01-05
Applicant: Intel Corporation
Inventor： Kyu-Oh Lee , Islam A. Salama , Ram S. Viswanath , Robert L. Sankman , Babak Sabi , Sri Chaitra Jyotsna Chavali
IPC: H01L23/00 , H01L23/13 , H01L23/48 , H01L25/10 , H01L23/498 , H01L25/065
Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.
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公开(公告)号：US20190221447A1
公开(公告)日：2019-07-18
申请号：US16305743
申请日：2016-06-30
Applicant: Intel Corporation
Inventor： Sri Chaitra Jyotsna Chavali , Siddharth K. Alur , Lillia May , Amanda E. Schuckman
IPC: H01L21/48 , H01L23/498
CPC classification number: H01L21/4857 , H01L23/49822 , H01L23/49827
Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
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公开(公告)号：US12062551B2
公开(公告)日：2024-08-13
申请号：US18118835
申请日：2023-03-08
Applicant: Intel Corporation
Inventor： Sri Chaitra Jyotsna Chavali , Siddharth K. Alur , Lilia May , Amanda E. Schuckman
IPC: H01L21/48 , H01L23/498
CPC classification number: H01L21/4857 , H01L23/49822 , H01L23/49827
Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
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Patent Agency Ranking
公开(公告)号：US11764150B2
公开(公告)日：2023-09-19
申请号：US16502025
申请日：2019-07-03
Applicant: Intel Corporation
Inventor： Sri Chaitra Jyotsna Chavali , Tarek Ibrahim , Wei-Lun Jen
IPC: H01L23/522 , H01L21/768 , H01L49/02 , H05K1/18 , H01L23/48 , H01L23/64
CPC classification number: H01L23/5227 , H01L21/76877 , H01L23/481 , H01L23/645 , H01L28/10 , H05K1/181 , H05K2201/1003
Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate having a core layer. An inductor may include a first coaxial line and a second coaxial line vertically through the core layer, and an interconnect within the package substrate coupling the first coaxial line and the second coaxial line. A first magnetic segment may surround the first coaxial line within the core layer, and a second magnetic segment may surround the second coaxial line within the core layer. In addition, a third magnetic segment may surround the interconnect and be coupled to the first magnetic segment and the second magnetic segment. Other embodiments may be described and/or claimed.
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公开(公告)号：US11107757B2
公开(公告)日：2021-08-31
申请号：US16855629
申请日：2020-04-22
Applicant: Intel Corporation
Inventor： Sanka Ganesan , William James Lambert , Zhichao Zhang , Sri Chaitra Jyotsna Chavali , Stephen Andrew Smith , Michael James Hill , Zhenguo Jiang
IPC: H01L21/48 , H01L23/498 , H01L23/31 , H05K1/18 , H01L23/00 , H01L25/10 , H01L25/065 , H05K7/02 , H01L21/56
Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
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公开(公告)号：US20210193579A1
公开(公告)日：2021-06-24
申请号：US16724907
申请日：2019-12-23
Applicant: Intel Corporation
Inventor： Sanka Ganesan , Robert L. Sankman , Sri Chaitra Jyotsna Chavali
IPC: H01L23/538 , H01L23/498 , H01L21/768
Abstract: Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die. The semiconductor package further includes an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.
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公开(公告)号：US20200221577A1
公开(公告)日：2020-07-09
申请号：US16819899
申请日：2020-03-16
Applicant: Intel Corporation
Inventor： Sri Chaitra Jyotsna Chavali , Amruthavalli Palavi Alur , Wei-Lun Kane Jen , Sriram Srinivasan
Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.
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公开(公告)号：US10658765B2
公开(公告)日：2020-05-19
申请号：US16021474
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Sri Chaitra Jyotsna Chavali , Sanka Ganesan , William J. Lambert , Debendra Mallik , Zhichao Zhang
Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.
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