公开(公告)号：US10121897B2

公开(公告)日：2018-11-06

申请号：US15660574

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/267 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08 ,  H01L29/201 ,  H01L29/207 ,  H01L29/417 ,  H01L29/45 ,  H01L29/16

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US10367093B2

公开(公告)日：2019-07-30

申请号：US15730542

申请日：2017-10-11

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H04B1/3827

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US09991172B2

公开(公告)日：2018-06-05

申请号：US14684732

申请日：2015-04-13

Applicant: Intel Corporation

Inventor： Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

IPC: H01L21/8238 ,  B82Y10/00 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/04 ,  H01L29/06 ,  H01L29/15 ,  H01L29/201 ,  H01L29/207 ,  H01L29/36 ,  H01L21/02

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/151 ,  H01L29/201 ,  H01L29/207 ,  H01L29/365

Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

公开(公告)号：US20180047846A1

公开(公告)日：2018-02-15

申请号：US15730542

申请日：2017-10-11

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H04B1/3827 ,  H01L29/06 ,  H01L29/10 ,  H01L29/267

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US20170170318A1

公开(公告)日：2017-06-15

申请号：US15442087

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L29/51 ,  H01L29/08 ,  H01L29/267 ,  H01L29/207

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20160197185A1

公开(公告)日：2016-07-07

申请号：US15069726

申请日：2016-03-14

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H04B1/3827 ,  H01L29/267 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract translation: 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。

公开(公告)号：US09385180B2

公开(公告)日：2016-07-05

申请号：US14576111

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/04 ,  H01L21/306 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/786

CPC classification number: H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.