公开(公告)号：US11031482B2

公开(公告)日：2021-06-08

申请号：US16889680

申请日：2020-06-01

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. Vacancies in the gate dielectric layer may be filled with capping layer material.

公开(公告)号：US09691856B2

公开(公告)日：2017-06-27

申请号：US14977479

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/15 ,  H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/51 ,  H01L29/12 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

公开(公告)号：US09614083B2

公开(公告)日：2017-04-04

申请号：US15179884

申请日：2016-06-10

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/267 ,  H01L29/10 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08 ,  H01L29/201 ,  H01L29/207 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20160197159A1

公开(公告)日：2016-07-07

申请号：US15067047

申请日：2016-03-10

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC: H01L29/51 ,  H01L29/49

CPC classification number: H01L29/513 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US09287380B2

公开(公告)日：2016-03-15

申请号：US14136589

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US10707319B2

公开(公告)日：2020-07-07

申请号：US15067047

申请日：2016-03-10

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.

公开(公告)号：US09806195B2

公开(公告)日：2017-10-31

申请号：US15069726

申请日：2016-03-14

Applicant: INTEL CORPORATION

Inventor： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H04B1/3827

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US09748391B2

公开(公告)日：2017-08-29

申请号：US15442087

申请日：2017-02-24

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/267 ,  H01L29/45 ,  H01L29/207 ,  H01L29/51 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US09548363B2

公开(公告)日：2017-01-17

申请号：US14302371

申请日：2014-06-11

Applicant: Intel Corporation

Inventor： Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Majumdar Amian ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/092 ,  H01L29/10 ,  H01L29/51

CPC classification number: H01L29/7784 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02546 ,  H01L21/823807 ,  H01L21/823885 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/15 ,  H01L29/157 ,  H01L29/205 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7783

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Abstract translation: CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。

公开(公告)号：US20160284847A1

公开(公告)日：2016-09-29

申请号：US15179884

申请日：2016-06-10

Applicant: Intel Corporation

Inventor： Robert S. Chau ,  Suman Datta ,  Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Matthew Metz

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L29/267 ,  H01L29/10 ,  H01L29/417 ,  H01L29/08 ,  H01L29/66 ,  H01L29/207 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/201 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.